Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 49 for “"CMOS circuits"”.
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Hierarchical test generation for CMOS circuits
… complementary metal oxide semiconductor (CMOS) circuits that effectively deals with these issues. Circuits are modeled using multi-level descriptions to handle large circuit sizes while maintaining an effective balance between accuracy and complexity. Object-oriented analysis and design …
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CMOS circuits for VCSEL-based optical IO
… the optical devices. This thesis presents 90nm CMOS front-end circuits which apply techniques to operate optical components beyond the intrinsic data rates imposed by these bandwidth limits. The differential TIA is based on a proposed core amplifier which uses cross-coupled NMOS cascodes to …
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Recognition of logic blocks in CMOS circuits
… the recognition of logic functional blocks in CMOS circuits is described in this thesis. A transistor level description of the circuit is assumed to be available. Predefined gates and logic blocks are extracted from such a description. This recognition procedure is a step towards raising the …
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Accurate power analysis of integrated CMOS circuits on gate level
… delay models, is not accurate enough for circuits with a significant logical circuit depth. The exact modelling of glitches on gate level is the main contribution of the thesis. First the different operation points of a gate are analysed for a glitch and an equilibrium state during the …
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Topics in Totally Self-Checking Circuits and Testable Cmos Circuits
… (TSC) circuit belongs to a class of circuits used for Concurrent Error Detection (CED) purposes. It consists of a functional circuit that has encoded inputs and outputs and a checker that monitors these outputs and gives an error indication. It is known that the traditional stuck-at …
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Switched inductor-capacitor CMOS circuits for radio frequency front-ends
Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2023-09-01 without embargo terms
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Methodology for Standby Leakage Power Reduction in Nanometer-Scale CMOS Circuits
<p>In nanometer-scale CMOS technology, leakage power has become a major component of the total power dissipation due to the downscaling of threshold voltage and gate oxide thickness. The leakage power consumption has received even more attention by increasing demand for mobile devices. Since mobile …
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A power reduction algorithm for combinatorial CMOS circuits using input disabling
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995.
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Optimization of high-speed CMOS circuits with analytical models for signal delay
… optimization of high speed and high integration CMOS VLSI circuit is greatly in need in deep submicron regime with respect to signal delay, chip area and power dissipation. Accurate modeling of signal path delays is of particular importance in optimization. Although circuit level simulators like …
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Modeling and simulation ofpMOSFET hot-carrier degradation in very large CMOS circuits
… tool for hot-carrier reliability analysis of CMOS VLSI circuits. This simulator should be able to handle very large submicrometer circuits accurately and efficiently.
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Fault simulation for supply current testing of bridging faults in CMOS circuits
… simulation that considers bridging faults in CMOS circuits that are tested using supply current monitoring. The discussion is restricted to single fault detection in CMOS combinational circuits. A CMOS circuit is represented by a two-level hierarchy. At the higher level, the circuit is …
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Resonant Wavelength Tuning and CMOS Circuits for Silicon Photonic Transmitters with Microring Modulators
… ER, or RLM—without requiring broadband circuits. Notably, this is the first controller designed to optimize RLM, a critical metric as MRMs gain prominence in 4-PAM modulation systems. Fourth, the design considerations of high-swing segmented cascode drivers, commonly used with MRMs, are …
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Low-Power CMOS Circuits for High-Performance Deep Submicron System on a Chip
Delay-locked loop (DLL)-based clock multipliers have several inherent advantages over conventional PLL-based clock multipliers. We propose a phase detector with reset circuitry and a new frequency multiplier to overcome the limited locking range and frequency multiplication problem of conventional …
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Design and Assembly of High-Temperature Signal Conditioning System on LTCC with Silicon Carbide CMOS Circuits
… and maintenance actually performed. The circuits for the signal conditioning system within the prototype module must survive the extreme temperature, pressure, and centrifugal force, or G-force, present in these settings. Multiple fabrication runs on different integrated silicon carbide …
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Power Estimation and Minimization of Digital Signal Processing Systems
… so far focussed on power dissipation in static CMOS circuits. Dynamic logic circuits are used in high-performance circuits due to their speed and area advantage over static CMOS circuits. In this thesis, we also present an optimization technique, termed clock-generating (CG) domino, for …
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Development of pick-and-place assembly techniques for monolithic optopill integration
… in the form of optopills on silicon CMOS circuits. Implementation of this technology poses several challenges such as recess filling and optopill bonding to the CMOS circuits. Research focused on establishing assembly techniques to overcome these challenges is performed. This thesis …
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A novel approach to embedding memory with crosstalk logic circuits for high performance applications
… with the logic to get built-in memory logic circuits that operate based on the crosstalk computing logic. These circuits are called Crosstalk Built-in Memory Logic (CBML) circuits which exploit the detrimental interconnect crosstalk and astutely turn this unwanted effect into a computing …
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Switch-Level Timing Simulation of Mos Vlsi Circuits
… tool for very-large-scale integrated (VLSI) circuits of metal-oxide-semiconductor (MOS) transistors. Such tools are called switch-level timing simulators and they provide adequate information on the performance of the circuits with a reasonable expenditure of computation time even for very …
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An investigation of sensitization conditions and test effectiveness for CMOS faults
Testing of digital circuits ensures functionality and reliability of the circuits. Previous research has addressed the inadequacies of conventional test methods based on line stuck-at faults in testing CMOS circuits and has proposed new test methods. In this research, the effectiveness of …
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