Abstract
dc:description.abstractAs the amount of data generated increases, so does the amount of data processing. However for some applications, a decision can be made using partial results obtained mid-computation. This research presents three MSB-first computation circuits which allow for early computation termination: an accumulator, a comparator and an arithmetic processing element. The circuits are constructed based on a novel carry propagation shift-register design. Results for various size inputs show a decrease in the number of clock cycles necessary to make a decision compared to existing techniques. In addition, the number of bits used in the computation is reduced, thereby decreasing the number of bits fetched from memory.
Degree
thesis:*- Name thesis:degree_name
- Doctor of Philosophy
- Level thesis:degree_level
- Campus Only Dissertation
- Discipline thesis:degree_discipline
- Electrical and Computer Engineering
- Year
- 2018
Author and committee
dc:creator, dc:contributor.*- Author dc:creator
-
- Hounsinou, Sena G
- Contributors dc:contributor
-
- Wang, Haibo
Identifiers
dc:identifier.*- Repository record dc:identifier
- https://opensiuc.lib.siu.edu/dissertations/1525
- OAI identifier oai:identifier
- oai:opensiuc.lib.siu.edu:dissertations-2529