PARALLEL DELAY FAULT GRADING HEURISTIC AND TESTING APPROACHES TO TROJAN IC DETECTION

A method to perform implicit path delay fault grading on GPGPU architectures is presented. Experimentally it is shown that it is over 1200x faster than a single-core implicit path delay fault grading method previously in the literature for higher accuracy and can be shown to scale to multiple GPGPUs. A post-silicon test pattern generation strategy to maximize the efficiency of broadside tests applied to a sequential design for a limited test budget is presented. Arguments are made for this approach for detecting embedded Trojan ICs in the next-state functions of a sequential system; they are based on a model where long sequences of inputs that are applied to the system in the functional mode can detect if Trojan hardware is triggered with high probability. An efficient and scalable input generation algorithm for broadside tests is introduced and its performance on ISCAS'89 and ITC'99 benchmark circuits is evaluated. A design-for-authentication strategy is presented for the insertion of cells to efficiently partition the combinational core of a circuit to detect inserted Trojan ICs. It is shown that the approach, combined with pseudo-exhaustive test pattern generation, guarantees detection in certain circumstances.

Name thesis:degree_name

Doctor of Philosophy

Level thesis:degree_level

Campus Only Dissertation

Discipline thesis:degree_discipline

Electrical and Computer Engineering

Year

2016

Author dc:creator

• Lenox, Joseph Daniel

Contributors dc:contributor

• Tragoudas, Spyros

• atpg
• bisa
• gpgpu
• trojan

Repository record dc:identifier

https://opensiuc.lib.siu.edu/dissertations/1315

OAI identifier oai:identifier

oai:opensiuc.lib.siu.edu:dissertations-2319