Optimization Techniques for Performance and Power Dissipation in Test and Validation

The high cost of chip testing makes testability an important aspect of any chip design. Two important testability considerations are addressed namely, the power consumption and test quality. The power consumption during shift is reduced by efficiently adding control logic to the design. Test quality is studied by determining the sensitization characteristics of a path to be tested. The path delay fault models have been used for the purpose of studying this problem. Another important aspect in chip design is performance validation, which is increasingly perceived as the major bottleneck in integrated circuit design. Given the synthesizable HDL code, the proposed technique will efficiently identify infeasible paths, subsequently, it determines the worst case execution time (WCET) in the HDL code.

Name thesis:degree_name

Doctor of Philosophy

Level thesis:degree_level

Campus Only Dissertation

Discipline thesis:degree_discipline

Electrical and Computer Engineering

Year

2012

Author dc:creator

• Jayaraman, Dheepakkumaran

Contributors dc:contributor

• Tragoudas, Spyros

• Binary Decision Diagrams
• Design-For-Test
• Low Power Shift
• Path Delay Faults
• Performance Validation
• Worst Case Analysis

Repository record dc:identifier

https://opensiuc.lib.siu.edu/dissertations/473

OAI identifier oai:identifier

oai:opensiuc.lib.siu.edu:dissertations-1473