{"id":{"repo_id":"siu-theses","oai_identifier":"oai:opensiuc.lib.siu.edu:dissertations-1473"},"canonical_url":"https://search.dev.ndltd.org/etd/siu-theses/oai:opensiuc.lib.siu.edu:dissertations-1473","repository":{"repo_id":"siu-theses","name":"Southern Illinois University","base_url":"https://opensiuc.lib.siu.edu/do/oai/"},"display":{"title":"Optimization Techniques for Performance and Power Dissipation in Test and Validation","abstract":"The high cost of chip testing makes testability an important aspect of any chip design. Two important testability considerations are addressed namely, the power consumption and test quality. The power consumption during shift is reduced by efficiently adding control logic to the design. Test quality is studied by determining the sensitization characteristics of a path to be tested. The path delay fault models have been used for the purpose of studying this problem. Another important aspect in chip design is performance validation, which is increasingly perceived as the major bottleneck in integrated circuit design. Given the synthesizable HDL code, the proposed technique will efficiently identify infeasible paths, subsequently, it determines the worst case execution time (WCET) in the HDL code.","abstract_html":"The high cost of chip testing makes testability an important aspect of any chip design. Two important testability considerations are addressed namely, the power consumption and test quality. The power consumption during shift is reduced by efficiently adding control logic to the design. Test quality is studied by determining the sensitization characteristics of a path to be tested. The path delay fault models have been used for the purpose of studying this problem. Another important aspect in chip design is performance validation, which is increasingly perceived as the major bottleneck in integrated circuit design. Given the synthesizable HDL code, the proposed technique will efficiently identify infeasible paths, subsequently, it determines the worst case execution time (WCET) in the HDL code.","abstract_has_math":false,"creators":["Jayaraman, Dheepakkumaran"],"institution":null,"degree_name":"Doctor of Philosophy","degree_level":"Campus Only Dissertation","degree_discipline":"Electrical and Computer Engineering","degree_department":null,"school":null,"contributors":["Tragoudas, Spyros"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2012,"date_issued":"2012-05-01T07:00:00Z","date_published":"2012-05-01T07:00:00Z","updated_at":"2026-07-24T04:33:54Z","subjects":["Binary Decision Diagrams","Design-For-Test","Low Power Shift","Path Delay Faults","Performance Validation","Worst Case Analysis"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://opensiuc.lib.siu.edu/dissertations/473","outbound_label":"Repository record","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Tragoudas, Spyros"]},{"key":"dc:creator","label":"Author","values":["Jayaraman, Dheepakkumaran"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical and Computer Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Campus Only Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Doctor of Philosophy"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Binary Decision Diagrams","Design-For-Test","Low Power Shift","Path Delay Faults","Performance Validation","Worst Case Analysis"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://opensiuc.lib.siu.edu/dissertations/473"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["The high cost of chip testing makes testability an important aspect of any chip design. Two important testability considerations are addressed namely, the power consumption and test quality. The power consumption during shift is reduced by efficiently adding control logic to the design. Test quality is studied by determining the sensitization characteristics of a path to be tested. The path delay fault models have been used for the purpose of studying this problem. Another important aspect in chip design is performance validation, which is increasingly perceived as the major bottleneck in integrated circuit design. Given the synthesizable HDL code, the proposed technique will efficiently identify infeasible paths, subsequently, it determines the worst case execution time (WCET) in the HDL code."]},{"key":"dc:title","label":"Title","values":["Optimization Techniques for Performance and Power Dissipation in Test and Validation"]}]}],"canonical_facts":{"dc:contributor":["Tragoudas, Spyros"],"dc:creator":["Jayaraman, Dheepakkumaran"],"dc:description.abstract":["The high cost of chip testing makes testability an important aspect of any chip design. Two important testability considerations are addressed namely, the power consumption and test quality. The power consumption during shift is reduced by efficiently adding control logic to the design. Test quality is studied by determining the sensitization characteristics of a path to be tested. The path delay fault models have been used for the purpose of studying this problem. Another important aspect in chip design is performance validation, which is increasingly perceived as the major bottleneck in integrated circuit design. Given the synthesizable HDL code, the proposed technique will efficiently identify infeasible paths, subsequently, it determines the worst case execution time (WCET) in the HDL code."],"dc:identifier":["https://opensiuc.lib.siu.edu/dissertations/473"],"dc:subject":["Binary Decision Diagrams","Design-For-Test","Low Power Shift","Path Delay Faults","Performance Validation","Worst Case Analysis"],"dc:title":["Optimization Techniques for Performance and Power Dissipation in Test and Validation"],"thesis:degree_discipline":["Electrical and Computer Engineering"],"thesis:degree_level":["Campus Only Dissertation"],"thesis:degree_name":["Doctor of Philosophy"]},"updated_at":"2026-07-24T04:33:54Z"}