Accurate power analysis of integrated CMOS circuits on gate level

The accurate calculation of a circuit's power consumption on gate level relies on an exact analysis of a circuit's activity (net activities). In combinatorial parts of a circuit many unnecessary transitions - and as a subset especially glitches - occur. The modelling of these glitches within the logic simulation, which use conventional delay models, is not accurate enough for circuits with a significant logical circuit depth. The exact modelling of glitches on gate level is the main contribution of the thesis. First the different operation points of a gate are analysed for a glitch and an equilibrium state during the glitch peak is found and experimentally evaluated. This equilibrium state is the base for the new glitch model. The model could be integrated into a new event driven simulation algorithm. The new developed simulator, which is based on the new simulation algorithm, is very efficient in terms of simulation performance and accuracy.

Level thesis:degree_level

thesis.doctoral

Grantor dc:publisher

Universität Oldenburg

Year

2001

Author dc:creator

• Rabe, Dirk

• [Keine Schlagwörter von Autor/in vergeben.]

Repository record source_url

http://oops.uni-oldenburg.de/341

OAI identifier oai:identifier

oai:oops.uni-oldenburg.de:341