{"id":{"repo_id":"oldenburg","oai_identifier":"oai:oops.uni-oldenburg.de:341"},"canonical_url":"https://search.dev.ndltd.org/etd/oldenburg/oai:oops.uni-oldenburg.de:341","repository":{"repo_id":"oldenburg","name":"Carl von Ossietzky Universität Oldenburg","base_url":"http://oops.uni-oldenburg.de/cgi/oai2"},"display":{"title":"Accurate power analysis of integrated CMOS circuits on gate level","abstract":"The accurate calculation of a circuit's power consumption on gate level relies on an exact analysis of a circuit's activity (net activities). In combinatorial parts of a circuit many unnecessary transitions - and as a subset especially glitches - occur. The modelling of these glitches within the logic simulation, which use conventional delay models, is not accurate enough for circuits with a significant logical circuit depth. The exact modelling of glitches on gate level is the main contribution of the thesis. First the different operation points of a gate are analysed for a glitch and an equilibrium state during the glitch peak is found and experimentally evaluated. This equilibrium state is the base for the new glitch model. The model could be integrated into a new event driven simulation algorithm. The new developed simulator, which is based on the new simulation algorithm, is very efficient in terms of simulation performance and accuracy.","abstract_html":"The accurate calculation of a circuit's power consumption on gate level relies on an exact analysis of a circuit's activity (net activities). In combinatorial parts of a circuit many unnecessary transitions - and as a subset especially glitches - occur. The modelling of these glitches within the logic simulation, which use conventional delay models, is not accurate enough for circuits with a significant logical circuit depth. The exact modelling of glitches on gate level is the main contribution of the thesis. First the different operation points of a gate are analysed for a glitch and an equilibrium state during the glitch peak is found and experimentally evaluated. This equilibrium state is the base for the new glitch model. The model could be integrated into a new event driven simulation algorithm. The new developed simulator, which is based on the new simulation algorithm, is very efficient in terms of simulation performance and accuracy.","abstract_has_math":false,"creators":["Rabe, Dirk"],"institution":"Universität Oldenburg","degree_name":null,"degree_level":"thesis.doctoral","degree_discipline":null,"degree_department":null,"school":null,"contributors":[],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2001,"date_issued":"2001-07-03","date_published":"2001-07-03","updated_at":"2026-07-27T20:27:22Z","subjects":["[Keine Schlagwörter von Autor/in vergeben.]"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://oops.uni-oldenburg.de/341","outbound_label":"Repository record","outbound_source":"source_url"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:creator","label":"Author","values":["Rabe, Dirk"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:publisher","label":"Institution","values":["BIS der Universität Oldenburg"]},{"key":"dc:type","label":"Dc Type","values":["doctoralThesis"]},{"key":"thesis:degree_level","label":"Degree Level","values":["thesis.doctoral"]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["Universität Oldenburg"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["[Keine Schlagwörter von Autor/in vergeben.]"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["The accurate calculation of a circuit's power consumption on gate level relies on an exact analysis of a circuit's activity (net activities). In combinatorial parts of a circuit many unnecessary transitions - and as a subset especially glitches - occur. The modelling of these glitches within the logic simulation, which use conventional delay models, is not accurate enough for circuits with a significant logical circuit depth. The exact modelling of glitches on gate level is the main contribution of the thesis. First the different operation points of a gate are analysed for a glitch and an equilibrium state during the glitch peak is found and experimentally evaluated. This equilibrium state is the base for the new glitch model. The model could be integrated into a new event driven simulation algorithm. The new developed simulator, which is based on the new simulation algorithm, is very efficient in terms of simulation performance and accuracy.","Die genaue Bestimmung des Schaltverhaltens (Netzaktivitäten) in einer Schaltung ist ein entscheidender Faktor bei der genauen Bestimmung der Verlustleistung auf Gatterebene. In kombinatorischen Schaltungsteilen treten viele unnötige Transitionen - und als Teilmenge hiervon insbesondere Glitches - auf. Die Modellierung dieser Glitches im Rahmen von Logiksimulationen mit konventionellen Verzögerungsmodellen ist nicht ausreichend für Schaltungen mit einer signifikanten Schaltungstiefe. Die genaue Modellierung der Glitches auf Gatterebene ist Hauptbestandteil der Arbeit. Zunächst werden die verschiedenen Arbeitspunkte eines Gatters beim Auftreten von Glitches analysiert und der Gleichgewichtszustand während des Glitchpeaks als Charakteristikum herausgestellt und experimentell evaluiert. Dieser Gleichgewichtszustand ist die Basis für das entwickelte Glitch-Modell. Das Modell konnte in einem neuartigen event-getriebenen Simulationsalgorithmus integriert und implementiert werden. Der Simulationsalgorithmus ist mit dem neuen Simulationsmodell besonders effizient bezüglich der Simulationsperformance und Simulationsgenauigkeit."]},{"key":"dc:format.medium","label":"Dc Format Medium","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Accurate power analysis of integrated CMOS circuits on gate level"]}]}],"canonical_facts":{"dc:creator":["Rabe, Dirk"],"dc:description.abstract":["The accurate calculation of a circuit's power consumption on gate level relies on an exact analysis of a circuit's activity (net activities). In combinatorial parts of a circuit many unnecessary transitions - and as a subset especially glitches - occur. The modelling of these glitches within the logic simulation, which use conventional delay models, is not accurate enough for circuits with a significant logical circuit depth. The exact modelling of glitches on gate level is the main contribution of the thesis. First the different operation points of a gate are analysed for a glitch and an equilibrium state during the glitch peak is found and experimentally evaluated. This equilibrium state is the base for the new glitch model. The model could be integrated into a new event driven simulation algorithm. The new developed simulator, which is based on the new simulation algorithm, is very efficient in terms of simulation performance and accuracy.","Die genaue Bestimmung des Schaltverhaltens (Netzaktivitäten) in einer Schaltung ist ein entscheidender Faktor bei der genauen Bestimmung der Verlustleistung auf Gatterebene. In kombinatorischen Schaltungsteilen treten viele unnötige Transitionen - und als Teilmenge hiervon insbesondere Glitches - auf. Die Modellierung dieser Glitches im Rahmen von Logiksimulationen mit konventionellen Verzögerungsmodellen ist nicht ausreichend für Schaltungen mit einer signifikanten Schaltungstiefe. Die genaue Modellierung der Glitches auf Gatterebene ist Hauptbestandteil der Arbeit. Zunächst werden die verschiedenen Arbeitspunkte eines Gatters beim Auftreten von Glitches analysiert und der Gleichgewichtszustand während des Glitchpeaks als Charakteristikum herausgestellt und experimentell evaluiert. Dieser Gleichgewichtszustand ist die Basis für das entwickelte Glitch-Modell. Das Modell konnte in einem neuartigen event-getriebenen Simulationsalgorithmus integriert und implementiert werden. Der Simulationsalgorithmus ist mit dem neuen Simulationsmodell besonders effizient bezüglich der Simulationsperformance und Simulationsgenauigkeit."],"dc:format.medium":["application/pdf"],"dc:publisher":["BIS der Universität Oldenburg"],"dc:subject":["[Keine Schlagwörter von Autor/in vergeben.]"],"dc:title":["Accurate power analysis of integrated CMOS circuits on gate level"],"dc:type":["doctoralThesis"],"thesis:degree_level":["thesis.doctoral"],"thesis:institution_name":["Universität Oldenburg"]},"updated_at":"2026-07-27T20:27:22Z"}