Design of an addressable memory controller.

The main memory is an essential subsystem in a Von Neumann type of stored program machine. Because of the speed gap existence between the processor and the main memor>% there has been a constant need to improve the main memor\' to achieve a better throughput. One method is to use a CAM(Content Addressable Memorv'). It is known as a \ery powerful facility for searching a particular item from a data array rather than from conventional memor\\ Investigated in this thesis are the discussion of CAM characteristics, timing analysis, CAM controller design and simulation results. The main results obtained in this thesis are timing characteristics of the CAM system and design considerations of the CAM controller

Department dc:contributor.department

Electrical and Computer Engineering

Year dc:date.issued

1987

Author dc:creator

• Ham, Byung Woon.

Advisor dc:contributor.advisor

• Lee, Chun-Hwa

Statement dc:rights

• Copyright is reserved by the copyright owner.

Language dc:language.iso

en_US

Handle dc:identifier.uri

https://hdl.handle.net/10945/22737

OAI identifier oai:identifier

oai:calhoun.nps.edu:10945/22737