{"id":{"repo_id":"nps","oai_identifier":"oai:calhoun.nps.edu:10945/22737"},"canonical_url":"https://search.dev.ndltd.org/etd/nps/oai:calhoun.nps.edu:10945/22737","repository":{"repo_id":"nps","name":"Naval Postgraduate School","base_url":"https://calhoun.nps.edu/server/oai/request"},"display":{"title":"Design of an addressable memory controller.","abstract":"The main memory is an essential subsystem in a Von Neumann type of stored program machine. Because of the speed gap existence between the processor and the main memor>% there has been a constant need to improve the main memor\\' to achieve a better throughput. One method is to use a CAM(Content Addressable Memorv'). It is known as a \\ery powerful facility for searching a particular item from a data array rather than from conventional memor\\\\ Investigated in this thesis are the discussion of CAM characteristics, timing analysis, CAM controller design and simulation results. The main results obtained in this thesis are timing characteristics of the CAM system and design considerations of the CAM controller","abstract_html":"The main memory is an essential subsystem in a Von Neumann type of stored program machine. Because of the speed gap existence between the processor and the main memor>% there has been a constant need to improve the main memor\\' to achieve a better throughput. One method is to use a CAM(Content Addressable Memorv'). It is known as a \\ery powerful facility for searching a particular item from a data array rather than from conventional memor\\\\ Investigated in this thesis are the discussion of CAM characteristics, timing analysis, CAM controller design and simulation results. The main results obtained in this thesis are timing characteristics of the CAM system and design considerations of the CAM controller","abstract_has_math":false,"creators":["Ham, Byung Woon."],"institution":null,"degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":"Electrical and Computer Engineering","school":null,"contributors":[],"advisors":["Lee, Chun-Hwa"],"committee_chairs":[],"committee_members":[],"year":1987,"date_issued":"1987","date_published":"1987","updated_at":"2026-07-27T20:25:53Z","subjects":[],"languages":["en_US"],"rights":["Copyright is reserved by the copyright owner."],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/10945/22737","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Lee, Chun-Hwa"]},{"key":"dc:contributor.department","label":"Department","values":["Electrical and Computer Engineering"]},{"key":"dc:creator","label":"Author","values":["Ham, Byung Woon."]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["March 1987"]},{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2012-11-27T00:28:27Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2012-11-27T00:28:27Z"]},{"key":"dc:date.issued","label":"Date","values":["1987"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["en_US"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright is reserved by the copyright owner."]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["https://hdl.handle.net/10945/22737"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["The main memory is an essential subsystem in a Von Neumann type of stored program machine. Because of the speed gap existence between the processor and the main memor>% there has been a constant need to improve the main memor\\' to achieve a better throughput. One method is to use a CAM(Content Addressable Memorv'). It is known as a \\ery powerful facility for searching a particular item from a data array rather than from conventional memor\\\\ Investigated in this thesis are the discussion of CAM characteristics, timing analysis, CAM controller design and simulation results. The main results obtained in this thesis are timing characteristics of the CAM system and design considerations of the CAM controller"]},{"key":"dc:title","label":"Title","values":["Design of an addressable memory controller."]}]}],"canonical_facts":{"dc:contributor.advisor":["Lee, Chun-Hwa"],"dc:contributor.department":["Electrical and Computer Engineering"],"dc:creator":["Ham, Byung Woon."],"dc:date":["March 1987"],"dc:date.accessioned":["2012-11-27T00:28:27Z"],"dc:date.available":["2012-11-27T00:28:27Z"],"dc:date.issued":["1987"],"dc:description.abstract":["The main memory is an essential subsystem in a Von Neumann type of stored program machine. Because of the speed gap existence between the processor and the main memor>% there has been a constant need to improve the main memor\\' to achieve a better throughput. One method is to use a CAM(Content Addressable Memorv'). It is known as a \\ery powerful facility for searching a particular item from a data array rather than from conventional memor\\\\ Investigated in this thesis are the discussion of CAM characteristics, timing analysis, CAM controller design and simulation results. The main results obtained in this thesis are timing characteristics of the CAM system and design considerations of the CAM controller"],"dc:identifier.uri":["https://hdl.handle.net/10945/22737"],"dc:language.iso":["en_US"],"dc:rights":["Copyright is reserved by the copyright owner."],"dc:title":["Design of an addressable memory controller."],"dc:type":["Thesis"]},"updated_at":"2026-07-27T20:25:53Z"}