Automated synthesis and NULL cycle reduction optimization for asynchronous NULL convention circuits using industry-standard CAD tools

"This dissertation focuses on developing algorithms for design automation of asynchronous NULL Convention Logic (NCL) circuits. Despite the numerous benefits of NCL circuits, such as reduced timing effort, power dissipation, and electro-magnetic interference (EMI), increased robustness, and better suitability for System-on-Chip (SoC) design, the lack of an automated design flow continues to prevent its widespread usage in the semiconductor industry. A novel circuit synthesis algorithm and an automated throughput enhancement technique have been developed and integrated into the industry-standard Mentor Graphics CAD tool suite, such that NCL circuits can be specified as high-level algorithmic descriptions and automatically synthesized and optimized, like their synchronous counterparts"--Abstract, page iv.

Name thesis:degree_name

Ph. D. in Computer Engineering

Grantor

University of Missouri--Rolla

Year dc:date.available

2016

Author dc:creator

• Bhaskaran, Bonita

• Computer Engineering

Repository record dc:identifier

https://scholarsmine.mst.edu/doctoral_dissertations/1730

OAI identifier oai:identifier

oai:scholarsmine.mst.edu:doctoral_dissertations-2732