{"id":{"repo_id":"must-thes","oai_identifier":"oai:scholarsmine.mst.edu:doctoral_dissertations-2732"},"canonical_url":"https://search.dev.ndltd.org/etd/must-thes/oai:scholarsmine.mst.edu:doctoral_dissertations-2732","repository":{"repo_id":"must-thes","name":"Missouri University of Science and Technology","base_url":"https://scholarsmine.mst.edu/do/oai/"},"display":{"title":"Automated synthesis and NULL cycle reduction optimization for asynchronous NULL convention circuits using industry-standard CAD tools","abstract":"\"This dissertation focuses on developing algorithms for design automation of asynchronous NULL Convention Logic (NCL) circuits. Despite the numerous benefits of NCL circuits, such as reduced timing effort, power dissipation, and electro-magnetic interference (EMI), increased robustness, and better suitability for System-on-Chip (SoC) design, the lack of an automated design flow continues to prevent its widespread usage in the semiconductor industry. A novel circuit synthesis algorithm and an automated throughput enhancement technique have been developed and integrated into the industry-standard Mentor Graphics CAD tool suite, such that NCL circuits can be specified as high-level algorithmic descriptions and automatically synthesized and optimized, like their synchronous counterparts\"--Abstract, page iv.","abstract_html":""This dissertation focuses on developing algorithms for design automation of asynchronous NULL Convention Logic (NCL) circuits. Despite the numerous benefits of NCL circuits, such as reduced timing effort, power dissipation, and electro-magnetic interference (EMI), increased robustness, and better suitability for System-on-Chip (SoC) design, the lack of an automated design flow continues to prevent its widespread usage in the semiconductor industry. A novel circuit synthesis algorithm and an automated throughput enhancement technique have been developed and integrated into the industry-standard Mentor Graphics CAD tool suite, such that NCL circuits can be specified as high-level algorithmic descriptions and automatically synthesized and optimized, like their synchronous counterparts"--Abstract, page iv.","abstract_has_math":false,"creators":["Bhaskaran, Bonita"],"institution":"University of Missouri--Rolla","degree_name":"Ph. D. in Computer Engineering","degree_level":null,"degree_discipline":null,"degree_department":null,"school":null,"contributors":[],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2016,"date_issued":"2016-02-10T08:00:00Z","date_published":"2016-02-10T08:00:00Z","updated_at":"2026-07-24T03:19:21Z","subjects":["Computer Engineering"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://scholarsmine.mst.edu/doctoral_dissertations/1730","outbound_label":"Repository record","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:creator","label":"Author","values":["Bhaskaran, Bonita"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.available","label":"Dc Date Available","values":["2016-02-10T08:00:00Z"]},{"key":"dc:type","label":"Dc Type","values":["Dissertation - Citation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph. D. in Computer Engineering"]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Missouri--Rolla"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Computer Engineering"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://scholarsmine.mst.edu/doctoral_dissertations/1730"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["\"This dissertation focuses on developing algorithms for design automation of asynchronous NULL Convention Logic (NCL) circuits. Despite the numerous benefits of NCL circuits, such as reduced timing effort, power dissipation, and electro-magnetic interference (EMI), increased robustness, and better suitability for System-on-Chip (SoC) design, the lack of an automated design flow continues to prevent its widespread usage in the semiconductor industry. A novel circuit synthesis algorithm and an automated throughput enhancement technique have been developed and integrated into the industry-standard Mentor Graphics CAD tool suite, such that NCL circuits can be specified as high-level algorithmic descriptions and automatically synthesized and optimized, like their synchronous counterparts\"--Abstract, page iv."]},{"key":"dc:title","label":"Title","values":["Automated synthesis and NULL cycle reduction optimization for asynchronous NULL convention circuits using industry-standard CAD tools"]}]}],"canonical_facts":{"dc:creator":["Bhaskaran, Bonita"],"dc:date.available":["2016-02-10T08:00:00Z"],"dc:description.abstract":["\"This dissertation focuses on developing algorithms for design automation of asynchronous NULL Convention Logic (NCL) circuits. Despite the numerous benefits of NCL circuits, such as reduced timing effort, power dissipation, and electro-magnetic interference (EMI), increased robustness, and better suitability for System-on-Chip (SoC) design, the lack of an automated design flow continues to prevent its widespread usage in the semiconductor industry. A novel circuit synthesis algorithm and an automated throughput enhancement technique have been developed and integrated into the industry-standard Mentor Graphics CAD tool suite, such that NCL circuits can be specified as high-level algorithmic descriptions and automatically synthesized and optimized, like their synchronous counterparts\"--Abstract, page iv."],"dc:identifier":["https://scholarsmine.mst.edu/doctoral_dissertations/1730"],"dc:subject":["Computer Engineering"],"dc:title":["Automated synthesis and NULL cycle reduction optimization for asynchronous NULL convention circuits using industry-standard CAD tools"],"dc:type":["Dissertation - Citation"],"thesis:degree_name":["Ph. D. in Computer Engineering"],"thesis:institution_name":["University of Missouri--Rolla"]},"updated_at":"2026-07-24T03:19:21Z"}