Reduction of process monitoring in semiconductor chip manufacturing

This thesis concerns in-line inspection scheduling policies in semiconductor chip manufacturing. Intel uses extensive monitoring (inspections) in the manufacturing process. While the inspections help safeguard process stability and boost manufacturing yield, they also account for a substantial fraction of the company's variable manufacturing costs. Intel is under pressure to cut inspections as a means of lowering these costs, and is currently pursuing an aggressive reduction policy. This thesis examines the risks and benefits of inspection reduction, and identifies competing considerations that affect the decision of how much inspection is appropriate. It proposes a decision algorithm to evaluate current inspection levels and determine the optimal frequency of inspections.

Department dc:contributor.department

Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

1999

Author dc:creator

• Amar, Ajay, 1964-

Advisor dc:contributor.advisor

• Arnold Barnett and Duane Boning.

• Sloan School of Management
• Electrical Engineering and Computer Science

Statement dc:rights

• M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/9742

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/9742