{"id":{"repo_id":"mit","oai_identifier":"oai:dspace.mit.edu:1721.1/9742"},"canonical_url":"https://search.dev.ndltd.org/etd/mit/oai:dspace.mit.edu:1721.1/9742","repository":{"repo_id":"mit","name":"MIT","base_url":"https://dspace.mit.edu/oai/request"},"display":{"title":"Reduction of process monitoring in semiconductor chip manufacturing","abstract":"This thesis concerns in-line inspection scheduling policies in semiconductor chip manufacturing. Intel uses extensive monitoring (inspections) in the manufacturing process. While the inspections help safeguard process stability and boost manufacturing yield, they also account for a substantial fraction of the company's variable manufacturing costs. Intel is under pressure to cut inspections as a means of lowering these costs, and is currently pursuing an aggressive reduction policy. This thesis examines the risks and benefits of inspection reduction, and identifies competing considerations that affect the decision of how much inspection is appropriate. It proposes a decision algorithm to evaluate current inspection levels and determine the optimal frequency of inspections.","abstract_html":"This thesis concerns in-line inspection scheduling policies in semiconductor chip manufacturing. Intel uses extensive monitoring (inspections) in the manufacturing process. While the inspections help safeguard process stability and boost manufacturing yield, they also account for a substantial fraction of the company&#x27;s variable manufacturing costs. Intel is under pressure to cut inspections as a means of lowering these costs, and is currently pursuing an aggressive reduction policy. This thesis examines the risks and benefits of inspection reduction, and identifies competing considerations that affect the decision of how much inspection is appropriate. It proposes a decision algorithm to evaluate current inspection levels and determine the optimal frequency of inspections.","abstract_has_math":false,"creators":["Amar, Ajay, 1964-"],"institution":"Massachusetts Institute of Technology","degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":"Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science","school":null,"contributors":[],"advisors":["Arnold Barnett and Duane Boning."],"committee_chairs":[],"committee_members":[],"year":1999,"date_issued":"1999","date_published":"1999","updated_at":"2026-07-22T22:21:39Z","subjects":["Sloan School of Management","Electrical Engineering and Computer Science"],"languages":["eng"],"rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."],"rights_urls":["http://dspace.mit.edu/handle/1721.1/7582"],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/1721.1/9742","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Arnold Barnett and Duane Boning."]},{"key":"dc:contributor.department","label":"Department","values":["Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science","Sloan School of Management"]},{"key":"dc:creator","label":"Author","values":["Amar, Ajay, 1964-"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2005-08-19T19:51:42Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2005-08-19T19:51:42Z"]},{"key":"dc:date.issued","label":"Date","values":["1999"]},{"key":"dc:publisher","label":"Institution","values":["Massachusetts Institute of Technology"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Sloan School of Management","Electrical Engineering and Computer Science"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."]},{"key":"dc:rights.uri","label":"Rights URI","values":["http://dspace.mit.edu/handle/1721.1/7582"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/1721.1/9742"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Thesis (M.B.A.)--Massachusetts Institute of Technology, Sloan School of Management; and (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1999.","Includes bibliographical references (leaf 40)."]},{"key":"dc:description.abstract","label":"Abstract","values":["This thesis concerns in-line inspection scheduling policies in semiconductor chip manufacturing. Intel uses extensive monitoring (inspections) in the manufacturing process. While the inspections help safeguard process stability and boost manufacturing yield, they also account for a substantial fraction of the company's variable manufacturing costs. Intel is under pressure to cut inspections as a means of lowering these costs, and is currently pursuing an aggressive reduction policy. This thesis examines the risks and benefits of inspection reduction, and identifies competing considerations that affect the decision of how much inspection is appropriate. It proposes a decision algorithm to evaluate current inspection levels and determine the optimal frequency of inspections."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["S.M.","M.B.A."]},{"key":"dc:format.mimetype","label":"Dc Format Mimetype","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Reduction of process monitoring in semiconductor chip manufacturing"]}]}],"canonical_facts":{"dc:contributor.advisor":["Arnold Barnett and Duane Boning."],"dc:contributor.department":["Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science","Sloan School of Management"],"dc:creator":["Amar, Ajay, 1964-"],"dc:date.accessioned":["2005-08-19T19:51:42Z"],"dc:date.available":["2005-08-19T19:51:42Z"],"dc:date.issued":["1999"],"dc:description":["Thesis (M.B.A.)--Massachusetts Institute of Technology, Sloan School of Management; and (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1999.","Includes bibliographical references (leaf 40)."],"dc:description.abstract":["This thesis concerns in-line inspection scheduling policies in semiconductor chip manufacturing. Intel uses extensive monitoring (inspections) in the manufacturing process. While the inspections help safeguard process stability and boost manufacturing yield, they also account for a substantial fraction of the company's variable manufacturing costs. Intel is under pressure to cut inspections as a means of lowering these costs, and is currently pursuing an aggressive reduction policy. This thesis examines the risks and benefits of inspection reduction, and identifies competing considerations that affect the decision of how much inspection is appropriate. It proposes a decision algorithm to evaluate current inspection levels and determine the optimal frequency of inspections."],"dc:description.degree":["S.M.","M.B.A."],"dc:format.mimetype":["application/pdf"],"dc:identifier.uri":["http://hdl.handle.net/1721.1/9742"],"dc:language.iso":["eng"],"dc:publisher":["Massachusetts Institute of Technology"],"dc:rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."],"dc:rights.uri":["http://dspace.mit.edu/handle/1721.1/7582"],"dc:subject":["Sloan School of Management","Electrical Engineering and Computer Science"],"dc:title":["Reduction of process monitoring in semiconductor chip manufacturing"],"dc:type":["Thesis"]},"updated_at":"2026-07-22T22:21:39Z"}