Circuit level synthesis for delta-sigma converters

Analog circuit design is a relatively complicated art that requires a high degree of erudition in the field. With this in mind, this thesis presents work on an analog circuit synthe­sis tool to minimize analog circuit design time. Specifically, the author has designed and implemented a discrete-time, one-bit, oversampling delta-sigma analog-to-digital modula­tor circuit synthesis tool in MATLAB script. With the parameters of center frequency, loop order, oversampling ratio, and minimum capacitor size, a user can utilize the pro­gram to generate a semi-optimized transistor level description of the modulator that can subsequently he used in SPICE. Parlaying Richard Schreier's work on a delta-sigma tool­box for MATLAB, the switched capacitor circuit contains robustly generated differential operational amplifiers and comparators. Furthermore, switched capacitors are scaled for minimal kT/C noise while switch sizes are synchronously adjusted to accommodate these values. Results of the SPICE simulations of the generated circuits compare favorably with the behaviorally predicted results.

Department dc:contributor.department

Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

1999

Author dc:creator

• Peng, Mark Shane, 1975-

Advisor dc:contributor.advisor

• Hae-Seung Lee.

• Electrical Engineering and Computer Science

Statement dc:rights

• M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/9722

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/9722