Towards low-power yet high-performance networks-on-chip

A network-on-chip (NoC), the de-facto communication backbone in manycore processors, consumes a significant portion of total chip power, competing against the computation cores for the limited power and thermal budget. On the other hand, overall system performance of manycore chips increasingly relies on on-chip latency and bandwidth as core counts scale. This thesis aims to design low-power yet high-performance NoCs through circuit and microarchitecture co-design contrary to the traditional approaches where NoCs sacrifice latency and/or bandwidth for low-power operation; then demonstrate such design concepts through test chip prototyping, enabling detailed measurements for rigorous analysis of the pros and cons of the proposed NoCs. The thesis starts with a 4x4 mesh NoC chip prototype that tries to simultaneously optimize energy, latency and throughput for all kinds of traffic (unicasts, multicasts and broadcasts). Its extensive experiment results make it possible to accurately analyze energy/performance benefits and timing/area overheads of the virtually bypassed, multicast-optimized router design; energy savings, area overheads and reduced reliability of the clocked low-swing datapath circuits; and a power gap between simulated estimations and measurement results. Next demonstrated is a link test chip of two clockless low-swing repeater designs, a self-resetting logic repeater (SRLR) optimized for transmission energy and a voltage-locked repeater (VLR) for transmission delay. This second chip prototype shows that the clockless, single-ended low-swing signaling of SRLRs armed with variation-robust circuit techniques has lower energy and smaller area than clocked, differential lowswing signaling. Featured with lower delay than full-swing repeaters, VLRs provide the fundamental building block to the single-cycle reconfigurable NoC that enables potential power saving at architecture level through single-cycle multi-hop asynchronous link traversal on dynamically configurable routes. The last one-third of this thesis explores a 3D-IC chip prototype of a throughsilicon via (TSV) interconnect that can support simultaneously bi-directional (SBD) signaling. While TSVs, as 3D-IC NoC links, offer an appealing solution to manycore architectures that require huge off-die bandwidth, existing TSV technologies impose considerable power and area overheads (using spare TSVs) to improve reliability. The proposed SBD TSV circuit shows better energy efficiency and smaller area than unidirectional TSVs, thus providing reliable 3D signaling within tight power/silicon budget. Such SBD signaling also enables configurable off-die bandwidth, and hence, can be the basis of a bandwidth-adaptive 3D NoC that efficiently supports highly dynamic traffic on manycore chips.

Department dc:contributor.department

Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2014

Author dc:creator

• Park, Sunghyun, Ph. D. Massachusetts Institute of Technology

Advisor dc:contributor.advisor

• Li-Shiuan Peh and Anantha P. Chandrakasan.

• Electrical Engineering and Computer Science.

Statement dc:rights

• M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/93776

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/93776