Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 23 for “"manycore"”.
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On-chip wireless manycore architectures
Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2023-12-01
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Multithreaded architectures for manycore throughput processors
… a set of tools we have developed for evaluating manycore accelerator architectures. The Rigel toolset includes an architectural simulator, LLVM-based compiler, parallel benchmarks, RTL models, and associated infrastructure scripts and toolflows. We have prepared an open-source release of portions …
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On-chip networks for manycore architecture
… effective programming models. A key component of manycore systems is the on-chip network, which faces increasing efficiency demands as the number of cores grows. In this thesis, we present three techniques for improving the efficiency of on-chip interconnects. First, we present PROM (Path-based, …
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Exploiting on-chip memory concurrency in 3d manycore architectures
The objective of this thesis is to optimize the uncore of 3D many-core architectures. More specifically, we note that technology trends point to large increases in memory-level concurrency. This in turn affects the design of the multi-core interconnect and organization of the memory hierarchy. The …
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Analyzing performance and usability of broadcast-based inter-core communication (ATAC) on manycore architecture
… of broadcast-based inter-core communication on manycore architecture. The problem of high communication cost on manycore architecture was tackled by a new architecture which allows ecient broadcasting by leveraging an on-chip optical network. I designed the new architecture and API for the new …
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Refrint: intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies
As manycores use dynamic energy ever more efficiently, static power consumption becomes a major concern. In particular, in a large manycore running at a low voltage, leakage in on-chip memory modules contributes substantially to the chip’s power draw. This is unfortunate given that, intuitively, …
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Towards low-power yet high-performance networks-on-chip
… (NoC), the de-facto communication backbone in manycore processors, consumes a significant portion of total chip power, competing against the computation cores for the limited power and thermal budget. On the other hand, overall system performance of manycore chips increasingly relies on on-chip …
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Validating performance and simplicity of highly concurrent data structures utilitizing the ATAC broadcast mechanism
… high performance on the next generation of manycore computers. The alternative model utilizes thread local memory and relies on the ATAC broadcast for inter-core communication, thus avoiding the complicated protocols that contemporary data structures use to mitigate contention. I explain the …
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High-speed modulation of resonant CMOS photonic modulators in deep-submicron CMOS
… performance, and the bandwidth demands of manycore systems are rising. Silicon photonics can lower the energy-per-bit of core-to-core and core-to-memory interconnects while simultaneously alleviating bandwidth bottlenecks. In this work, methods of controlling the amount of charge entering …
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Cooperative hierarchical resource management for efficient composition of parallel software
… be a thriving software industry in the upcoming manycore era unless programmers can compose arbitrary parallel codes without sacrificing performance. We believe that the efficient composition of parallel codes is best achieved by exposing unvirtualized hardware resources and sharing these …
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Distributed naming in a factored operating system
… (fos) is a new operating system design for manycore and cloud computers. In fos, OS services are separated from application code and run on distinct cores. Furthermore, each service is split into a fleet, or parallel set of cooperating processes that communicate using messages. Applications …
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Architecting, programming, and evaluating an on-chip incoherent multi-processor memory hierarchy
… is a recently-proposed extreme-scale manycore that radically simplifies the architecture, and proposes a cluster-based on-chip memory hierarchy without hardware cache coherence. Programming for such an environment, which can use scratchpads or incoherent caches, is challenging. Hence, …
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Methodologies, Architectures, and Prototypes for Scaling On- and Off-Chip Interconnects
… first part of this thesis focuses on OCNs for manycore architectures. I first present PyOCN, a unified Python-based framework for modeling, testing, and evaluating on-chip networks, which vertically integrates multiple research methodologies and enables productive design space exploration of …
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The Challenges of Non-linear Parameters and Variables in Automatic Loop Parallelisation
With the rise of manycore processors, parallelism is becoming a mainstream necessity. Unfortunately, parallel programming is inherently more difficult than sequential programming; therefore, techniques for automatic parallelisation will become indispensable. We aim at extending the well-known …
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Adaptation of the MapReduce programming framework to compute-intensive data-analytics kernels
… accelerator, whether GPUs (NVIDIA or AMD), other manycore architectures (like Intel Larrabee or MIC) or even heterogeneous chips (AMD Fusion or IBM Cell processor), there is a fundamental condition imposed on the software, namely the increased sensitivity to locality. As a result, the common theme …
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Exploiting tightly-coupled cores
As we move steadily through the multicore era, and the number of processing cores on each chip continues to rise, parallel computation becomes increasingly important. However, parallelising an application is often difficult because of dependencies between different regions of code which require …
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Advanced System-Scale and Chip-Scale Interconnection Networks for Ultrascale Systems
The path towards realizing next-generation petascale and exascale computing is increasingly dependent on building supercomputers with unprecedented numbers of processors. Given the rise of multicore processors, the number of network endpoints both on-chip and off-chip is growing exponentially, with …
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Optimization of Test and Design-for-Testability Solutions for Many-Core System-on-Chip Designs
… problems related to test-delivery in manycore SOCs that are assembled using a scalable and flexible integration platform. The proposed research has led to theoretical insights, simulation results, and a set of test and design-for-test methods to make testing effective and feasible from …
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Optimización de algoritmos bioinspirados en sistemas heterogéneos CPU-GPU.
… desarrollado numerosas contribuciones multicore, manycore, heterogeneidad, dark silicon, etc, para tratar de paliar esta ralentización computacional, dejando en segundo plano otros factores fundamentales en la resolución de problemas como la programabilidad, la fiabilidad, la precisión, etc. El …
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Scalable and flexible bulk architecture
… this environment, a major bottleneck in a large manycore with directory-based coherence is the chunk commit operation. The reason is that a chunk must appear to commit all of its writes atomically — even though the addresses written by the chunk belong to different, distributed directory modules. …
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