A ballistic transport model for HEMTs and III-V MOSFETs

As silicon MOSFETs keep scaling down in size, the continued improvement on their logic performance is threated by their fundamental physical limits. With silicon approaching these limits, MOSFETs designed with III-V semiconductors have emerged as promising candidates to replace them. The low-effective mass of various III-V materials such as InGaAs and InAs allow both faster and more power efficient performance. One of the key challenges, particularly as devices continue to shrink, is to understand the important of non-idealities in FET structures. High-electron mobility transistors, or HEMTs, are III-V Quantum-Well FETs that we can use to explore many issues of relevance to future III-V MOSFETs. HEMTs are worthwhile transistors in their own right, but are also simpler than III-V MOSFETs and therefore allow a more thorough exploration into the basic transport physics of a quantum-well III-V device. We know from HEMT experimental data that electrons travel ballistically at gate lengths of 30- 40 nm, suggesting that a ballistic transport model will only become more accurate as channel lengths are scaled down to 10 nm. We would like to investigate to what extent this is true in III-V MOSFETs, and also to study the impact of short channel effects and other parasitics inherent to a III-V design. To accomplish these goals, we have developed a flexible transistor model in MATLAB based on a ballistic theory of transport. We will first verify the model with HEMT experimental data coming from devices fabricated at MIT, and then focus our attention on peculiarities specific to III-V MOSFETs, namely a buried-channel design and the presence of traps at the oxide-semiconductor interface. We will use the model to extract the trap density as a function of energy, and then make measurements independent of interface trap effects to extract the 2D sheet carrier concentration and mobility, two figures of merit important in characterizing FET devices. The ability to correctly model and predict device behavior will help identify the problems ahead that need improvement in the iterations of future device fabrication.

Department dc:contributor.department

Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2013

Author dc:creator

• Warnock, Shireen M

Advisor dc:contributor.advisor

• Jesús A. del Alamo.

• Electrical Engineering and Computer Science.

Statement dc:rights

• M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/85520

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/85520