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Massachusetts Institute of Technology

Nano-scale metal contacts for future III-V CMOS

Abstract

dc:description.abstract

As modem transistors continue to scale down in size, conventional Si CMOS is reaching its physical limits and alternative technologies are needed to extend Moore's law. Among different candidates, MOSFETs with a III-V compound semiconductor channel are of great interest. Specifically, designs with an InGaAs channel have shown promising results for N type MOSFETs. In a new generation of III-V MOSFETs, one of the key challenges is to shrink device footprint while improving transistor's electrical performance. For future technology nodes, the gate length of MOSFETs needs to shrink below 10 nm, and the source and drain contacts must also decrease to a comparable dimension. A concern about contact scaling is the increase of source resistance. It is predicted that the source resistance will increase exponentially when the contact length is decreased to the nanometer scale regime. In order to understand the issues associated with source contact scaling to the nanometer regime, we have developed a fabrication process for nanometer scale TLM test structures to InGaAs/InAlAs heterostructures for MOSFETs. To analyze these structures, we have also developed a 2D circuit network. After measuring the fabricated devices, the model has been used to extract the relevant electrical parameters that characterize these structures. We have obtained a specific contact resistivity of (0. 116 +/- 0.058) [omega] - um². For Mo/n+-InGaAs contacts, to the best of our knowledge, this is the lowest value reported to date. The fabrication process and the theoretical model presented in this study should help future III-V CMOS scaling research and development.

Degree

thesis:*
Department dc:contributor.department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.
Grantor dc:publisher
Massachusetts Institute of Technology
Year dc:date.issued
2012

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Guo, Alex
Advisor dc:contributor.advisor
  • Jesús A. del Alamo.

Subjects

dc:subject × 1

Rights

dc:rights
Statement dc:rights
  • M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
Language dc:language.iso
eng

Identifiers

dc:identifier.*
Handle dc:identifier.uri
http://hdl.handle.net/1721.1/78460
OAI identifier oai:identifier
oai:dspace.mit.edu:1721.1/78460

Chain of custody

source
Harvested from
MIT
Base URL
dspace.mit.edu/oai/request
Last updated
2026-07-22
Source record
OAI-PMH GetRecord
citation

Guo, Alex. Nano-scale metal contacts for future III-V CMOS. Massachusetts Institute of Technology, 2012. http://hdl.handle.net/1721.1/78460