{"id":{"repo_id":"mit","oai_identifier":"oai:dspace.mit.edu:1721.1/78460"},"canonical_url":"https://search.dev.ndltd.org/etd/mit/oai:dspace.mit.edu:1721.1/78460","repository":{"repo_id":"mit","name":"MIT","base_url":"https://dspace.mit.edu/oai/request"},"display":{"title":"Nano-scale metal contacts for future III-V CMOS","abstract":"As modem transistors continue to scale down in size, conventional Si CMOS is reaching its physical limits and alternative technologies are needed to extend Moore's law. Among different candidates, MOSFETs with a III-V compound semiconductor channel are of great interest. Specifically, designs with an InGaAs channel have shown promising results for N type MOSFETs. In a new generation of III-V MOSFETs, one of the key challenges is to shrink device footprint while improving transistor's electrical performance. For future technology nodes, the gate length of MOSFETs needs to shrink below 10 nm, and the source and drain contacts must also decrease to a comparable dimension. A concern about contact scaling is the increase of source resistance. It is predicted that the source resistance will increase exponentially when the contact length is decreased to the nanometer scale regime. In order to understand the issues associated with source contact scaling to the nanometer regime, we have developed a fabrication process for nanometer scale TLM test structures to InGaAs/InAlAs heterostructures for MOSFETs. To analyze these structures, we have also developed a 2D circuit network. After measuring the fabricated devices, the model has been used to extract the relevant electrical parameters that characterize these structures. We have obtained a specific contact resistivity of (0. 116 +/- 0.058) [omega] - um². For Mo/n+-InGaAs contacts, to the best of our knowledge, this is the lowest value reported to date. The fabrication process and the theoretical model presented in this study should help future III-V CMOS scaling research and development.","abstract_html":"As modem transistors continue to scale down in size, conventional Si CMOS is reaching its physical limits and alternative technologies are needed to extend Moore's law. Among different candidates, MOSFETs with a III-V compound semiconductor channel are of great interest. Specifically, designs with an InGaAs channel have shown promising results for N type MOSFETs. In a new generation of III-V MOSFETs, one of the key challenges is to shrink device footprint while improving transistor's electrical performance. For future technology nodes, the gate length of MOSFETs needs to shrink below 10 nm, and the source and drain contacts must also decrease to a comparable dimension. A concern about contact scaling is the increase of source resistance. It is predicted that the source resistance will increase exponentially when the contact length is decreased to the nanometer scale regime. In order to understand the issues associated with source contact scaling to the nanometer regime, we have developed a fabrication process for nanometer scale TLM test structures to InGaAs/InAlAs heterostructures for MOSFETs. To analyze these structures, we have also developed a 2D circuit network. After measuring the fabricated devices, the model has been used to extract the relevant electrical parameters that characterize these structures. We have obtained a specific contact resistivity of (0. 116 +/- 0.058) [omega] - um². For Mo/n+-InGaAs contacts, to the best of our knowledge, this is the lowest value reported to date. The fabrication process and the theoretical model presented in this study should help future III-V CMOS scaling research and development.","abstract_has_math":false,"creators":["Guo, Alex"],"institution":"Massachusetts Institute of Technology","degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":"Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.","school":null,"contributors":[],"advisors":["Jesús A. del Alamo."],"committee_chairs":[],"committee_members":[],"year":2012,"date_issued":"2012","date_published":"2012","updated_at":"2026-07-22T22:22:22Z","subjects":["Electrical Engineering and Computer Science."],"languages":["eng"],"rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."],"rights_urls":["http://dspace.mit.edu/handle/1721.1/7582"],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/1721.1/78460","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Jesús A. del Alamo."]},{"key":"dc:contributor.department","label":"Department","values":["Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science."]},{"key":"dc:contributor.other","label":"Dc Contributor Other","values":["Massachusetts Institute of Technology. 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Specifically, designs with an InGaAs channel have shown promising results for N type MOSFETs. In a new generation of III-V MOSFETs, one of the key challenges is to shrink device footprint while improving transistor's electrical performance. For future technology nodes, the gate length of MOSFETs needs to shrink below 10 nm, and the source and drain contacts must also decrease to a comparable dimension. A concern about contact scaling is the increase of source resistance. It is predicted that the source resistance will increase exponentially when the contact length is decreased to the nanometer scale regime. In order to understand the issues associated with source contact scaling to the nanometer regime, we have developed a fabrication process for nanometer scale TLM test structures to InGaAs/InAlAs heterostructures for MOSFETs. To analyze these structures, we have also developed a 2D circuit network. After measuring the fabricated devices, the model has been used to extract the relevant electrical parameters that characterize these structures. We have obtained a specific contact resistivity of (0. 116 +/- 0.058) [omega] - um². For Mo/n+-InGaAs contacts, to the best of our knowledge, this is the lowest value reported to date. The fabrication process and the theoretical model presented in this study should help future III-V CMOS scaling research and development."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["S.M."]},{"key":"dc:title","label":"Title","values":["Nano-scale metal contacts for future III-V CMOS"]}]}],"canonical_facts":{"dc:contributor.advisor":["Jesús A. del Alamo."],"dc:contributor.department":["Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science."],"dc:contributor.other":["Massachusetts Institute of Technology. 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For future technology nodes, the gate length of MOSFETs needs to shrink below 10 nm, and the source and drain contacts must also decrease to a comparable dimension. A concern about contact scaling is the increase of source resistance. It is predicted that the source resistance will increase exponentially when the contact length is decreased to the nanometer scale regime. In order to understand the issues associated with source contact scaling to the nanometer regime, we have developed a fabrication process for nanometer scale TLM test structures to InGaAs/InAlAs heterostructures for MOSFETs. To analyze these structures, we have also developed a 2D circuit network. After measuring the fabricated devices, the model has been used to extract the relevant electrical parameters that characterize these structures. We have obtained a specific contact resistivity of (0. 116 +/- 0.058) [omega] - um². For Mo/n+-InGaAs contacts, to the best of our knowledge, this is the lowest value reported to date. The fabrication process and the theoretical model presented in this study should help future III-V CMOS scaling research and development."],"dc:description.degree":["S.M."],"dc:identifier.uri":["http://hdl.handle.net/1721.1/78460"],"dc:language.iso":["eng"],"dc:publisher":["Massachusetts Institute of Technology"],"dc:rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."],"dc:rights.uri":["http://dspace.mit.edu/handle/1721.1/7582"],"dc:subject":["Electrical Engineering and Computer Science."],"dc:title":["Nano-scale metal contacts for future III-V CMOS"],"dc:type":["Thesis"]},"updated_at":"2026-07-22T22:22:22Z"}