Performance limits of RF power CMOS

Wireless and mobile communication systems have become ubiquitous in our daily life. The need for higher bandwidth and thus higher speed and data rates in wireless communications has prompted the exploration of millimeter-wave frequencies. Some of the applications in this regime include high-speed wireless local area networks and high data rate personal area networks at 60 GHz, automotive collision avoidance radar at 77 GHz and millimeter-wave imaging at 94 GHz. Most of these applications are cost sensitive and require high levels of integration to reduce system size. The tremendous improvement in the frequency response of state-of-the-art deeply scaled CMOS technologies has made them an ideal candidate for millimeter-wave applications. A few research groups have already demonstrated single chip CMOS radios at 60 GHz. However, the design of power amplifiers in CMOS still remains a significant challenge because of the low breakdown voltage of deep submicron CMOS technologies. Power levels from 60 GHz power amplifiers have been limited to around 15 dBm with power-added efficiencies in the 10-20% range, despite the use of multiple gain stages and power combining techniques. In this work, we have studied the RF power potential of commercial 65 nm and 45 nm CMOS technologies. We have mapped the frequency, power and efficiency limitations of these technologies and identified the physical mechanisms responsible for these limitations. We also present a simple analytical model that allows circuit designers to estimate the maximum power obtainable from their designs for a given efficiency. The model uses only the DC bias point and on-resistance of the device as inputs and contains no adjustable parameters. We have demonstrated a record output power density of 210 mW/mm and power-added efficiency in excess of 75% at VDs = 1.1 V and f = 2 GHz on 45 nm CMOS devices. This record power performance was made possible through careful device layout for minimized parasitic resistances and capacitances. Total output power approaching 70 mW was measured on 45 nm CMOS devices by increasing the device width to 640 gm. However, we find that the output power scales non-ideally with device width because of an increase in normalized on-resistance in the wide devices. PAE also decreases with increasing device width because of degradation in f. in the wide devices. Additionally PAE decreases as the measurement frequency increases, though the output power remains constant with increasing frequency. Small-signal equivalent circuit extractions on these devices suggest that the main reason for the degradation in the normalized output power and PAE with increasing device width is the non-ideal scaling of parasitic gate and drain resistances in the wide devices.

Department dc:contributor.department

Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2011

Author dc:creator

• Gogineni, Usha, 1975-

Advisor dc:contributor.advisor

• Jesús A. del Alamo.

• Electrical Engineering and Computer Science.

Statement dc:rights

• M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/63070

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/63070