Design study of a novel computer instruction execution unit

The goal of the "Fresh Breeze Project" is to develop a multi-core chip architecture that supports a better programming model for parallel computing. This architecture combines simultaneous multithreading, a global shared address space, no memory update, and a cycle-free heap to provide a platform for robust, general-purpose, parallel computation. These design choices help simplify classically hard problems such as memory coherency, control flow, and synchronization. An HDL implementation of the core execution unit of a single processing core (many cores are on a single chip) forms the basis of further simulation and synthesis. The design must first be broken down into functional logic blocks and translated into hardware modules. The language Bluespec Verilog allows this description to be constructed in terms of higher-level "guarded atomic actions" triggered by a rule based system.

Department dc:contributor.department

Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2008

Author dc:creator

• Chiou, Albert (Albert C.)

Advisor dc:contributor.advisor

• Jack Dennis.

• Electrical Engineering and Computer Science.

Statement dc:rights

• M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/45998

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/45998