{"id":{"repo_id":"mit","oai_identifier":"oai:dspace.mit.edu:1721.1/45998"},"canonical_url":"https://search.dev.ndltd.org/etd/mit/oai:dspace.mit.edu:1721.1/45998","repository":{"repo_id":"mit","name":"MIT","base_url":"https://dspace.mit.edu/oai/request"},"display":{"title":"Design study of a novel computer instruction execution unit","abstract":"The goal of the \"Fresh Breeze Project\" is to develop a multi-core chip architecture that supports a better programming model for parallel computing. This architecture combines simultaneous multithreading, a global shared address space, no memory update, and a cycle-free heap to provide a platform for robust, general-purpose, parallel computation. These design choices help simplify classically hard problems such as memory coherency, control flow, and synchronization. An HDL implementation of the core execution unit of a single processing core (many cores are on a single chip) forms the basis of further simulation and synthesis. The design must first be broken down into functional logic blocks and translated into hardware modules. The language Bluespec Verilog allows this description to be constructed in terms of higher-level \"guarded atomic actions\" triggered by a rule based system.","abstract_html":"The goal of the "Fresh Breeze Project" is to develop a multi-core chip architecture that supports a better programming model for parallel computing. This architecture combines simultaneous multithreading, a global shared address space, no memory update, and a cycle-free heap to provide a platform for robust, general-purpose, parallel computation. These design choices help simplify classically hard problems such as memory coherency, control flow, and synchronization. An HDL implementation of the core execution unit of a single processing core (many cores are on a single chip) forms the basis of further simulation and synthesis. The design must first be broken down into functional logic blocks and translated into hardware modules. The language Bluespec Verilog allows this description to be constructed in terms of higher-level "guarded atomic actions" triggered by a rule based system.","abstract_has_math":false,"creators":["Chiou, Albert (Albert C.)"],"institution":"Massachusetts Institute of Technology","degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":"Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.","school":null,"contributors":[],"advisors":["Jack Dennis."],"committee_chairs":[],"committee_members":[],"year":2008,"date_issued":"2008","date_published":"2008","updated_at":"2026-07-22T22:20:55Z","subjects":["Electrical Engineering and Computer Science."],"languages":["eng"],"rights":["M.I.T. theses are protected by copyright. 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