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Massachusetts Institute of Technology

Transport enhancement techniques for nanoscale MOSFETs

Abstract

dc:description.abstract

Over the past two decades, intrinsic MOSFET delay has been scaled commensurate with the scaling of the dimensions. To extend this historical trend in the future, careful analysis of what determines the transistor performance is required. In this work, a new delay metric is first introduced that better captures the interplay of the main technology parameters, and employed to study the historical trends of the performance scaling and to quantify the requirements for the continuous increase of the performance in the future. It is shown that the carrier velocity in the channel has been the main driver for the improved transistor performance with scaling. A roadmapping exercise is presented and it is shown that new channel materials are needed to lever carrier velocity beyond what is achieved with uniaxially strained silicon, along with dramatic reduction in the device parasitics. Such innovations are needed as early as the 32-nm node to avoid the otherwise counter-scaling of the performance. The prospects and limitations of various approaches that are being pursued to increase the carrier velocity and thereby the transistor performance are then explored. After introducing the basics of the transport in nanoscale MOSFETs, the impact of channel material and strain configuration on electron and hole transport are examined. Uniaixal tensile strain in silicon is shown to be very promising to enhance electron transport as long as higher strain levels can be exerted on the device. Calculations and analysis in this work demonstrate that in uniaxially strained silicon, virtual source velocity depends more strongly on the mobility than previously believed and the modulation of the effective mass under uniaxial strain is responsible for this string dependence.

Degree

thesis:*
Department dc:contributor.department
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Grantor dc:publisher
Massachusetts Institute of Technology
Year dc:date.issued
2008

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Khakifirooz, Ali
Advisor dc:contributor.advisor
  • Dimitri A. Antoniadis.

Subjects

dc:subject × 1

Rights

dc:rights
Statement dc:rights
  • M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
Language dc:language.iso
eng

Identifiers

dc:identifier.*
Handle dc:identifier.uri
http://hdl.handle.net/1721.1/42907
OAI identifier oai:identifier
oai:dspace.mit.edu:1721.1/42907

Chain of custody

source
Harvested from
MIT
Base URL
dspace.mit.edu/oai/request
Last updated
2026-07-22
Source record
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citation

Khakifirooz, Ali. Transport enhancement techniques for nanoscale MOSFETs. Massachusetts Institute of Technology, 2008. http://hdl.handle.net/1721.1/42907