Variation-aware placement tool for Field Programmable Gate Array devices

Introduction: As semiconductor technologies become more advanced, process variations within microelectronic devices, including variations in channel length or in oxide thickness, play a much more important role with regards to circuit delay and leakage power dissipation. These process variations cause variability in circuit performance characteristics that can be minimized by improving process control techniques, resulting in more predictable behavior. However, if we are concerned with programmable logic devices like FPGAs affected by variation, the circuit designer in the field has no control over or knowledge about the manner in which process variations affect the device and the final circuit implementation. Our research here is aimed at developing and incorporating process variation models into circuit design and implementation tools for FPGAs. With variation aware tools, programmable logic device users will have the opportunity to produce circuit implementations that are fully optimized for performance given the presence of process variations.

Department dc:contributor.department

Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2007

Author dc:creator

• Perez, Christopher E

Advisor dc:contributor.advisor

• Arif Rahman and Charles G. Sodini.

• Electrical Engineering and Computer Science.

Statement dc:rights

• M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/41664

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/41664