{"id":{"repo_id":"mit","oai_identifier":"oai:dspace.mit.edu:1721.1/41664"},"canonical_url":"https://search.dev.ndltd.org/etd/mit/oai:dspace.mit.edu:1721.1/41664","repository":{"repo_id":"mit","name":"MIT","base_url":"https://dspace.mit.edu/oai/request"},"display":{"title":"Variation-aware placement tool for Field Programmable Gate Array devices","abstract":"Introduction: As semiconductor technologies become more advanced, process variations within microelectronic devices, including variations in channel length or in oxide thickness, play a much more important role with regards to circuit delay and leakage power dissipation. These process variations cause variability in circuit performance characteristics that can be minimized by improving process control techniques, resulting in more predictable behavior. However, if we are concerned with programmable logic devices like FPGAs affected by variation, the circuit designer in the field has no control over or knowledge about the manner in which process variations affect the device and the final circuit implementation. Our research here is aimed at developing and incorporating process variation models into circuit design and implementation tools for FPGAs. With variation aware tools, programmable logic device users will have the opportunity to produce circuit implementations that are fully optimized for performance given the presence of process variations.","abstract_html":"Introduction: As semiconductor technologies become more advanced, process variations within microelectronic devices, including variations in channel length or in oxide thickness, play a much more important role with regards to circuit delay and leakage power dissipation. These process variations cause variability in circuit performance characteristics that can be minimized by improving process control techniques, resulting in more predictable behavior. However, if we are concerned with programmable logic devices like FPGAs affected by variation, the circuit designer in the field has no control over or knowledge about the manner in which process variations affect the device and the final circuit implementation. Our research here is aimed at developing and incorporating process variation models into circuit design and implementation tools for FPGAs. With variation aware tools, programmable logic device users will have the opportunity to produce circuit implementations that are fully optimized for performance given the presence of process variations.","abstract_has_math":false,"creators":["Perez, Christopher E"],"institution":"Massachusetts Institute of Technology","degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":"Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.","school":null,"contributors":[],"advisors":["Arif Rahman and Charles G. Sodini."],"committee_chairs":[],"committee_members":[],"year":2007,"date_issued":"2007","date_published":"2007","updated_at":"2026-07-22T22:22:13Z","subjects":["Electrical Engineering and Computer Science."],"languages":["eng"],"rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."],"rights_urls":["http://dspace.mit.edu/handle/1721.1/7582"],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/1721.1/41664","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Arif Rahman and Charles G. Sodini."]},{"key":"dc:contributor.department","label":"Department","values":["Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science."]},{"key":"dc:contributor.other","label":"Dc Contributor Other","values":["Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science."]},{"key":"dc:creator","label":"Author","values":["Perez, Christopher E"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2008-05-19T16:06:46Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2008-05-19T16:06:46Z"]},{"key":"dc:date.issued","label":"Date","values":["2007"]},{"key":"dc:publisher","label":"Institution","values":["Massachusetts Institute of Technology"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Electrical Engineering and Computer Science."]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."]},{"key":"dc:rights.uri","label":"Rights URI","values":["http://dspace.mit.edu/handle/1721.1/7582"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/1721.1/41664"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.","Includes bibliographical references (p. 97-98)."]},{"key":"dc:description.abstract","label":"Abstract","values":["Introduction: As semiconductor technologies become more advanced, process variations within microelectronic devices, including variations in channel length or in oxide thickness, play a much more important role with regards to circuit delay and leakage power dissipation. These process variations cause variability in circuit performance characteristics that can be minimized by improving process control techniques, resulting in more predictable behavior. However, if we are concerned with programmable logic devices like FPGAs affected by variation, the circuit designer in the field has no control over or knowledge about the manner in which process variations affect the device and the final circuit implementation. Our research here is aimed at developing and incorporating process variation models into circuit design and implementation tools for FPGAs. With variation aware tools, programmable logic device users will have the opportunity to produce circuit implementations that are fully optimized for performance given the presence of process variations."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["M.Eng."]},{"key":"dc:title","label":"Title","values":["Variation-aware placement tool for Field Programmable Gate Array devices"]}]}],"canonical_facts":{"dc:contributor.advisor":["Arif Rahman and Charles G. Sodini."],"dc:contributor.department":["Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science."],"dc:contributor.other":["Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science."],"dc:creator":["Perez, Christopher E"],"dc:date.accessioned":["2008-05-19T16:06:46Z"],"dc:date.available":["2008-05-19T16:06:46Z"],"dc:date.issued":["2007"],"dc:description":["Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.","Includes bibliographical references (p. 97-98)."],"dc:description.abstract":["Introduction: As semiconductor technologies become more advanced, process variations within microelectronic devices, including variations in channel length or in oxide thickness, play a much more important role with regards to circuit delay and leakage power dissipation. These process variations cause variability in circuit performance characteristics that can be minimized by improving process control techniques, resulting in more predictable behavior. However, if we are concerned with programmable logic devices like FPGAs affected by variation, the circuit designer in the field has no control over or knowledge about the manner in which process variations affect the device and the final circuit implementation. Our research here is aimed at developing and incorporating process variation models into circuit design and implementation tools for FPGAs. With variation aware tools, programmable logic device users will have the opportunity to produce circuit implementations that are fully optimized for performance given the presence of process variations."],"dc:description.degree":["M.Eng."],"dc:identifier.uri":["http://hdl.handle.net/1721.1/41664"],"dc:language.iso":["eng"],"dc:publisher":["Massachusetts Institute of Technology"],"dc:rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."],"dc:rights.uri":["http://dspace.mit.edu/handle/1721.1/7582"],"dc:subject":["Electrical Engineering and Computer Science."],"dc:title":["Variation-aware placement tool for Field Programmable Gate Array devices"],"dc:type":["Thesis"]},"updated_at":"2026-07-22T22:22:13Z"}