Clock division as a power saving strategy in a system constrained by high transmission frequency and low data rate

Systems are often restricted to have higher transmission frequency than required by their data rates. Possible constraints include channel attenuation, power requirements, and backward compatibility. As a result these systems have unused band- width, leading to inefficient use of power. In this thesis, I propose to slow the internal operating frequency of a cochlear implant receiver in order to reduce the internal power consumption by more than a factor of ten. I have created a new data encoding scheme, called "N-[pi] Shift Encoding", which makes clock division a viable solution. This clock division technique can be applied to other similarly constrained systems.

Department dc:contributor.department

Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2005

Author dc:creator

• Selbst, Andrew D. (Andrew David)

Advisor dc:contributor.advisor

• Rahul Sarpeshkar.

• Electrical Engineering and Computer Science.

Statement dc:rights

• M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/33360

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/33360