Hardware implementation of the Advanced Encryption Standard

This project implements a hardware solution to the Advanced Encryption Standard (AES) algorithm and interfaces to IBM's CoreConnect Bus Architecture. The project is IBM SoftCore compliant, is synthesized to the .18 micron CMOS double-well technology, runs at 133 MHz, and is approximately 706K for the 16x128 bit buffer implementation and 874K gates for the 32x128 bit buffer implementation. Data can be encrypted and decrypted at a throughput of 1Gbps. The work described in the paper was completed as a part of MIT's VI-A program in the ASIC Digital Cores III group of the Microelectronics Division at IBM.

Department dc:contributor.department

Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2003

Author dc:creator

• Maurer, Jennifer (Jennifer Robin), 1979-

Advisor dc:contributor.advisor

• Jonathan H. Raymond and Donald E. Troxel.

• Electrical Engineering and Computer Science.

Statement dc:rights

• M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/29732

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/29732