{"id":{"repo_id":"mit","oai_identifier":"oai:dspace.mit.edu:1721.1/29732"},"canonical_url":"https://search.dev.ndltd.org/etd/mit/oai:dspace.mit.edu:1721.1/29732","repository":{"repo_id":"mit","name":"MIT","base_url":"https://dspace.mit.edu/oai/request"},"display":{"title":"Hardware implementation of the Advanced Encryption Standard","abstract":"This project implements a hardware solution to the Advanced Encryption Standard (AES) algorithm and interfaces to IBM's CoreConnect Bus Architecture. The project is IBM SoftCore compliant, is synthesized to the .18 micron CMOS double-well technology, runs at 133 MHz, and is approximately 706K for the 16x128 bit buffer implementation and 874K gates for the 32x128 bit buffer implementation. Data can be encrypted and decrypted at a throughput of 1Gbps. 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