PLL-based active optical clock distribution

Reducing the timing uncertainty associated with clock edges has become an exceedingly difficult problem as clock frequencies in high-performance processors increase past several gigahertz. Absolute quantities of skew and jitter that were insignificant at lower frequencies now consume an increasingly large percentage of each clock cycle and directly reduce the time available for logic propagation. Processor designers currently employ several types of electrical deskew mechanisms to combat this problem in order to delay the inevitable need for more radical clocking solutions. Optical clock distribution has the potential to deliver extremely high precision global clocks across large chips. However, traditional transimpedance amplifier approaches to optical-electrical conversion introduce so much timing uncertainty that the accuracy gained through optical global distribution is lost at the global-to-local clock domain interface. This thesis analyzes the feasibility of a phase-locked loop (PLL) based approach to the optical-electrical clock signal conversion. The proposed small-signal current-steering optical-electrical phase detector extracts timing information from the optical reference without explicit optical-electrical conversion. This phase detector is integrated with a loop filter, LC VCO, and frequency divider to form a complete optical-electrical PLL system capable of generating 1.6 GHz local electrical clocks from a 200 MHz global optical reference. The insights gained through the design and implementation of this system are used as the basis for a broader analysis of the advantages and challenges of PLL-based optical clock distribution systems.

Department dc:contributor.department

Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2004

Author dc:creator

• Kern, Alexandra M., 1979-

Advisor dc:contributor.advisor

• Anantha P. Chandrakasan.

• Electrical Engineering and Computer Science.

Statement dc:rights

• M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

en_US

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/28721

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/28721