Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 39 for “"Phase locked loop (PLL)"”.
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An integer-N charge-pump phase-locked loop with controllable phase offset
In a phase-locked loop (PLL), the phase-offset is a result from non-idealities that usually need to be minimized to reduce the reference spurs at the output. However, in certain applications such as multi-buses, we would like to control this offset so we can align the clock with the data. This …
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Automatic calibration of modulated fractional-N frequency synthesizers
… in service automatic calibration of a modulated phase locked loop (PLL) frequency synthesizer has been developed. Phase/frequency modulation is accomplished by modulating the feedback divide value in a phase locked loop frequency synthesizer. A digital precompensation filter is used to extend the …
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Design and analysis of a high-rate acoustic link for underwater video transmission
… modems, prototype acoustic modems based on phase coherent modulation/detection have demonstrated successful transmission at 30 kbps over a deep water channel. The key to bridging the remaining gap between the bit-rate needed for video transmission and that supported by the acoustic channel …
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Dissertation review on a new control perspective on phase locked loops
The technique of phase-locked loop (PLL), an essential means for online frequency detection of incoming signal, which is widely used in our modern day communication system. PLL is traditionally viewed as a non-linear feedback control loop that will automatically locks the adjustable frequency of a …
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Phase-locked loop using time-based integral control
… the time-based techniques in the context of phase-locked loop (PLL) implementation. Many studies of the topic have been performed in the past. Functioning as an effective replacement of passive capacitors, time-based integrators using oscillators prove to be more area efficient and highly …
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A Novel Passive Islanding Detection Method Based on Phase-Locked Loop
… existing passive IDMs, and an analysis of the phase-locked loop (PLL) behaviour under grid-connected and islanded conditions using its quasi-static model. Based on the results of these studies, a novel passive IDM is developed that utilizes the PLL error to detect islanding with a small NDZ and …
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PLL-based active optical clock distribution
… This thesis analyzes the feasibility of a phase-locked loop (PLL) based approach to the optical-electrical clock signal conversion. The proposed small-signal current-steering optical-electrical phase detector extracts timing information from the optical reference without explicit …
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Fast Chirped Signals for a TDMA Ultrasonic Indoor Positioning System
… of ultrasonic signals is presented. Nonlinear phase characteristics of ultrasonic transducers introduce a frequency deviation in ultrasonic signals. By sweeping at very fast rates, a large spike in the deviation is introduced. The artefacts observable in instantaneous frequency estimations are …
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Extending the Flexibility of an RFIC Transceiver Through Modifications to the External Circuit
… identified were implementation of a phase locked detector, various methods for extending the FSK data rate limitations of the transmitter, improving the phase noise of the VCO, and the implementation of a fractional-N synthesizer using the RF2905 internal phase-locked loop (PLL) …
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Design and Evaluation of a Photovoltaic Inverter with Grid-Tracking and Grid-Forming Controls
… control scheme, which is based on the dq phase-locked-loop- (PLL-) oriented vector control. Synchronous machines inherently synchronize to the grid and largely partake in the stabilization of the grid frequency during power system dynamics. The purpose of this thesis is primarily to …
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Análise de estabilidade para inversores LCL conectados à rede elétrica baseada em expressões analíticas e estimativas de impedâncias no domínio síncrono DQ
… The results obtained with a hardware-in-the-loop (HIL) system and an experimental setup validate the developed models. They confirm that the Zqq component of the matrix behaves like a negative resistor within the bandwidth of the control phase-locked loop (PLL), similar to what is reported …
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Fast all-digital carrier synchronization techniques for linear modulation formats
… suitable for linear modulation schemes ( M -ary phaseshift-keying ( M -PSK) and M -ary quadrature amplitude modulation ( M -QAM)). Carrier synchronization is studied because, in passband communications, carrier phase and frequency offsets, due to modem oscillator discrepancies and distances …
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Underwater acoustic communication over Doppler spread channels
… Doppler spread is found. By using the DFE with a phase locked loop (PLL) suboptimal system behavior is found, and this is verified on real data. In the case of a simple Doppler shift the cross-ambiguity function is used to estimate the shift, and the received signal is phase rotated to compensate …
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Phase-locked loop, delay-locked loop, and linear decorrelating detector for asynchronous multirate DS-CDMA system
The performance of phase synchronization and code tracking of a digital phase-locked loop (PLL) and delay-locked loop (DLL), respectively, is investigated in wideband asynchronous multirate DS-CDMA system. Dynamic Partial Correlation (DPC) method is proposed to evaluate the autocorrelation and its …
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Analysis and design of high order digital phase locked loops
The Phase Locked Loop (PLL) is an important component of many electronic devices; it can be employed as a frequency synthesizer, for clock data recovery, and as amplitude and frequency demodulators. It is an inherently nonlinear closed loop feedback system; the nonlinearity is due mainly to the …
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Design and modelling of clock and data recovery integrated circuit in 130 nm CMOS technology for 10 Gb/s serial data communications
… and implementation of a fully monolithic 10 Gb/s phase and frequency-locked loop based clock and data recovery (PFLL-CDR) integrated circuit, as well as the Verilog-A modeling of an asynchronous serial link based chip to chip communication system incorporating the proposed concept. The proposed …
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Design of all digital phase-locked loop in serial link communication
… speed links, clocking circuitry is vital, and phase-locked loop (PLL) is at the heart of every on-chip clocking circuit. The clocking circuitry needs to be robust, low-power and fast in order to fulfill the increasing demand for high data rate links. The performance of the input/output (I/O) …
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Clock synthesizer design with analog and digital phase locked loop
… clocking circuit used in high-speed links is the Phase-Locked Loop (PLL). This thesis provides an in-depth analysis of basic analog PLL theory, architecture and transistor level design. The all-digital counterpart of the analog PLL will also be presented for its ultra low power and small …
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Key receiver circuits for digital beamforming in millimeter-wave imaging
… we investigate key components for an active phased array imaging system operating at 77GHz that performs purely digital beamforming. Each element in the phased array has an antenna and processor that measures the phase and amplitude of the received signal. The focus of this thesis is the …
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Analysis and Implementation of a Novel Single Channel Direction Finding Algorithm on a Software Radio Platform
… such as MUSIC [1][2] and ESPRIT use simultaneous phase information from each antenna to estimate the angle-of-arrival of the signal of interest. In many scenarios (e.g., hand-held systems), however, multiple receivers are impractical. Thus, single channel techniques are of interest, particularly …
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