A user interface for algorithmic debug

The hardware verification pipeline for server-scale system on chips (SoCs) is as complex as the SoCs themselves. Intel's Validation Acceleration through Shared Expertise (VASE) tool allows teams at different stages of the verification pipeline-from subsystem development to system integration-to share key architectural, test, and debug knowledge. By enabling system experts to automate the detection of common simulation failures, VASE allows the engineers who are inheriting a subsystem to instantly have access to their expertise whenever a simulation failure occurs. The VASE tool has the potential to greatly increase validation efficiency, but its adoption into Intel's verification work flow is put at risk by usability issues. To address these shortcomings, I developed a user interface that facilitates the creation of the simulation failure debug decision trees by the system experts. This GUI aims to increase usability for tree definition and manipulation, to enforce node subtree coherence across all trees, and to provide a tree building solution which scales with the complexity of the system.

Department dc:contributor.department

Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2018

Author dc:creator

• Rodriguez Gallegos, Juan Miguel

Advisor dc:contributor.advisor

• Arvind and Beth Markey.

• Electrical Engineering and Computer Science.

Statement dc:rights

• MIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/119773

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/119773