{"id":{"repo_id":"mit","oai_identifier":"oai:dspace.mit.edu:1721.1/119773"},"canonical_url":"https://search.dev.ndltd.org/etd/mit/oai:dspace.mit.edu:1721.1/119773","repository":{"repo_id":"mit","name":"MIT","base_url":"https://dspace.mit.edu/oai/request"},"display":{"title":"A user interface for algorithmic debug","abstract":"The hardware verification pipeline for server-scale system on chips (SoCs) is as complex as the SoCs themselves. Intel's Validation Acceleration through Shared Expertise (VASE) tool allows teams at different stages of the verification pipeline-from subsystem development to system integration-to share key architectural, test, and debug knowledge. By enabling system experts to automate the detection of common simulation failures, VASE allows the engineers who are inheriting a subsystem to instantly have access to their expertise whenever a simulation failure occurs. The VASE tool has the potential to greatly increase validation efficiency, but its adoption into Intel's verification work flow is put at risk by usability issues. To address these shortcomings, I developed a user interface that facilitates the creation of the simulation failure debug decision trees by the system experts. This GUI aims to increase usability for tree definition and manipulation, to enforce node subtree coherence across all trees, and to provide a tree building solution which scales with the complexity of the system.","abstract_html":"The hardware verification pipeline for server-scale system on chips (SoCs) is as complex as the SoCs themselves. Intel's Validation Acceleration through Shared Expertise (VASE) tool allows teams at different stages of the verification pipeline-from subsystem development to system integration-to share key architectural, test, and debug knowledge. By enabling system experts to automate the detection of common simulation failures, VASE allows the engineers who are inheriting a subsystem to instantly have access to their expertise whenever a simulation failure occurs. The VASE tool has the potential to greatly increase validation efficiency, but its adoption into Intel's verification work flow is put at risk by usability issues. To address these shortcomings, I developed a user interface that facilitates the creation of the simulation failure debug decision trees by the system experts. This GUI aims to increase usability for tree definition and manipulation, to enforce node subtree coherence across all trees, and to provide a tree building solution which scales with the complexity of the system.","abstract_has_math":false,"creators":["Rodriguez Gallegos, Juan Miguel"],"institution":"Massachusetts Institute of Technology","degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":"Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.","school":null,"contributors":[],"advisors":["Arvind and Beth Markey."],"committee_chairs":[],"committee_members":[],"year":2018,"date_issued":"2018","date_published":"2018","updated_at":"2026-07-22T22:21:32Z","subjects":["Electrical Engineering and Computer Science."],"languages":["eng"],"rights":["MIT theses are protected by copyright. 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They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission."]},{"key":"dc:rights.uri","label":"Rights URI","values":["http://dspace.mit.edu/handle/1721.1/7582"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/1721.1/119773"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2018.","Cataloged from PDF version of thesis.","Includes bibliographical references (pages 32-33)."]},{"key":"dc:description.abstract","label":"Abstract","values":["The hardware verification pipeline for server-scale system on chips (SoCs) is as complex as the SoCs themselves. Intel's Validation Acceleration through Shared Expertise (VASE) tool allows teams at different stages of the verification pipeline-from subsystem development to system integration-to share key architectural, test, and debug knowledge. By enabling system experts to automate the detection of common simulation failures, VASE allows the engineers who are inheriting a subsystem to instantly have access to their expertise whenever a simulation failure occurs. The VASE tool has the potential to greatly increase validation efficiency, but its adoption into Intel's verification work flow is put at risk by usability issues. To address these shortcomings, I developed a user interface that facilitates the creation of the simulation failure debug decision trees by the system experts. This GUI aims to increase usability for tree definition and manipulation, to enforce node subtree coherence across all trees, and to provide a tree building solution which scales with the complexity of the system."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["M. Eng."]},{"key":"dc:title","label":"Title","values":["A user interface for algorithmic debug"]}]}],"canonical_facts":{"dc:contributor.advisor":["Arvind and Beth Markey."],"dc:contributor.department":["Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science."],"dc:contributor.other":["Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science."],"dc:creator":["Rodriguez Gallegos, Juan Miguel"],"dc:date.accessioned":["2018-12-18T20:04:03Z"],"dc:date.available":["2018-12-18T20:04:03Z"],"dc:date.issued":["2018"],"dc:description":["Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2018.","Cataloged from PDF version of thesis.","Includes bibliographical references (pages 32-33)."],"dc:description.abstract":["The hardware verification pipeline for server-scale system on chips (SoCs) is as complex as the SoCs themselves. Intel's Validation Acceleration through Shared Expertise (VASE) tool allows teams at different stages of the verification pipeline-from subsystem development to system integration-to share key architectural, test, and debug knowledge. By enabling system experts to automate the detection of common simulation failures, VASE allows the engineers who are inheriting a subsystem to instantly have access to their expertise whenever a simulation failure occurs. The VASE tool has the potential to greatly increase validation efficiency, but its adoption into Intel's verification work flow is put at risk by usability issues. To address these shortcomings, I developed a user interface that facilitates the creation of the simulation failure debug decision trees by the system experts. This GUI aims to increase usability for tree definition and manipulation, to enforce node subtree coherence across all trees, and to provide a tree building solution which scales with the complexity of the system."],"dc:description.degree":["M. Eng."],"dc:identifier.uri":["http://hdl.handle.net/1721.1/119773"],"dc:language.iso":["eng"],"dc:publisher":["Massachusetts Institute of Technology"],"dc:rights":["MIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission."],"dc:rights.uri":["http://dspace.mit.edu/handle/1721.1/7582"],"dc:subject":["Electrical Engineering and Computer Science."],"dc:title":["A user interface for algorithmic debug"],"dc:type":["Thesis"]},"updated_at":"2026-07-22T22:21:32Z"}