Design of experiments on a semiconductor plasma ashing process : methods and analysis

Characterizing and controlling process variations in semiconductor manufacturing processes is crucial to ensure the extremely low defect and scrap rates that are needed for semiconductor manufacturing companies to maximize profitability. As semiconductor device critical dimensions become smaller and chips become more complex, and with customers inquiring about process capability metrics to make sure they get the highest quality product, there is a need for chip manufacturers to thoroughly analyze and define their process capabilities. The work in this thesis done in collaboration with Analog Devices Inc., a leading chip manufacturer, shows how the concept of design of experiments (DOE) and statistical regression modeling techniques can be implemented in a practical industrial setting to rigorously understand and mathematically characterize process variations in a semiconductor fabrication process (plasma ashing). New approaches are introduced to Analog Devices Inc. in calculating wafer statistics. Methodologies are developed that will help the company to choose the right experimental designs based on the objective (e.g. accurate prediction of the response variable, process optimization, process robustness, etc.) while taking into account the process, time, and cost constraints. Multiple regression modeling techniques are utilized to analyze the outcomes of the experiment and the results of these techniques are compared to each other in order to choose the right model needed to satisfy the objective. The statistical software JMP is used to tease out subtle implications of the outcomes of the DOE and formulate hypotheses about any anomalies. The DOEs are performed on two Gasonics Aura 3010 machines that carry out the plasma ashing process using the same process parameters in order to highlight not only the similarities but also the differences in the machines which come from factors like the intrinsic build and state of the machines. The findings and results identify opportunities for the development of new process improvement strategies, faster root cause analysis of failures, methods to systematically calibrate new equipment, update standard operating procedures, and opportunities for machine matching. The purpose of this thesis is to serve as a pedagogical document and template for the process engineers at Analog Devices Inc. in the future to perform DOEs on other processes and machines in the fabrication center.

Department dc:contributor.department

Massachusetts Institute of Technology. Department of Mechanical Engineering.

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2016

Author dc:creator

• Nerurkar, Tanay Rahul

Advisor dc:contributor.advisor

• Duane S. Boning.

• Mechanical Engineering.

Statement dc:rights

• MIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/107024

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/107024