Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 69 for “"process variations"”.
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Techniques for VLSI Circuit Optimization Considering Process Variations
… has increased the transistor's susceptibility to process variations in nanometer very large scale integrated (VLSI) circuits. The effects of such variations are having a huge impact on performance and hence the timing yield of the integrated circuits. The circuit optimization objectives namely …
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Delay Testing in Nanoscale Technology under Process Variations
In modern CMOS technology, process variations have significantly increased impact on the circuit behavior with continuously scaled transistor sizes. Manufactured devices tend to have different performances due to parameter variations during manufacturing and in the operating context. Conventional …
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Modeling silicon photonics process variations using ring resonator devices
… systems using extensions to traditional CMOS process technologies. With silicon technologies being used to transmit light, there exists a need by designers to understand the performance of standard silicon photonic elements and the deviations that may arise in actual production. Drop-in models …
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Statistical Modeling of the Effects of Process Variations on Silicon Photonics
… Silicon photonics leverages existing CMOS processes and fabrication infrastructure, making its components suffer from the process variations present in CMOS technology. Long and repetitive simulations are required to understand the effect of these variations, largely due to the lack of …
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Methods for compact modeling of process variations in silicon photonics devices
… being developed with extensions to existing CMOS processes, and are growing in complexity. Silicon photonics designs are evaluated in simulation using similar methods to those used for CMOS transistor and circuit designs; simulation models for common silicon-based photonics structures and devices …
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Assessing Approximate Arithmetic Designs in the presence of Process Variations and Voltage Scaling
… priorities, innovative approaches which reduce processor energy consumption are sought. Approximate arithmetic units are one of the avenues whereby significant energy savings can be achieved. Approximation of fundamental arithmetic units is achieved by judiciously reducing the number of …
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The effect of treatment process variations on the thickening and dewatering characteristics of water plant sludges
… The effluent turbidity was monitored to evaluate process modifications. Sludge thickening and dewatering characteristics improved with reductions in the coagulation pH, increases in the influent turbidity levels, and/or reductions in the coagulant dose/influent turbidity ratio. Sludge floc/ …
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Characterizing within-die and die-to-die delay variations introduced By process variations and SOI history effect
Variations in delay caused by within-die and die-to-die process variations and SOI history effect increase timing margins and reduce performance. In order to develop mitigation techniques to reduce the detrimental effects of delay variations, particularly those that occur within-die, new methods of …
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Variation-aware placement tool for Field Programmable Gate Array devices
… semiconductor technologies become more advanced, process variations within microelectronic devices, including variations in channel length or in oxide thickness, play a much more important role with regards to circuit delay and leakage power dissipation. These process variations cause variability …
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SSTA design methodology for low voltage operation
Statistical process variations have long been an important design issue. But until recently, process variations have been global process variations, i.e., transistor parameters may vary from die to die but are constant within a die. With transistor geometries shrinking below 65nm, however, a new …
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VLSI Physical Design for Manufacturability and Reliability
… algorithms. In Chapter 5, buffer insertion under process variations is discussed in details. We proved that buffer insertion is not sensitive to process variations both theoretically and practically. In Chapter 6 and 7, design techniques are presented to improve the manufacturability. We present a …
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Probing Control of Glucose Feeding in Escherichia coli Cultivations
… source that usually is glucose. In fed-batch processes the glucose feed rate can be manipulated to avoid acetate formation, but most feeding strategies require considerable process knowledge to handle process variations. On-line measurements for the relevant process variables are far from …
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Adjoint Methods and Inverse Modeling for Process Variation Analysis in Silicon Photonics
… the field of integrated photonics, manufacturing process variation studies are required to launch the many photonic applications to mass production and commercial use. Specifically, we need models that predict the impact of process variations on photonic circuits, and extraction of process …
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In-Memory Computing Architecture for Deep Learning Acceleration
… accelerators, large cache demands for multi-core processors, system performance, energy, and efficiency. In this thesis, I present my research works that address these challenges by leveraging emerging memory and logic devices, as well as advanced integration technologies. In the first work, I …
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Design of experiments on a semiconductor plasma ashing process : methods and analysis
Characterizing and controlling process variations in semiconductor manufacturing processes is crucial to ensure the extremely low defect and scrap rates that are needed for semiconductor manufacturing companies to maximize profitability. As semiconductor device critical dimensions become smaller …
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Design of robust spin-transfer torque magnetic random access memories for ultralow power high performance on-chip cache applications
… failures of STT-MRAMs are degraded further under process variations. The focus of this dissertation is to optimize the yield of STT- MRAMs under process variations by employing device-circuit-architecture co-design techniques. A devices-to-systems simulation framework was developed to evaluate the …
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Intrinsic PUFs for commodity devices
… identifiers from low level manufacturing process variations. <br/><br/>In this thesis several novel designs and improvements for Intrinsic PUFs are proposed and experimentally validated, with an aim towards achieving practical Intrinsic PUFs for ubiquitous underlying technologies that …
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Non-invasive IC tomography using spatial correlations
… post-silicon characterization of the gate-level variations in a manufactured Integrated Circuit (IC). The estimated characteristics are based on the power and the delay measurements that are affected by the process variations. The power (delay) variations are spatially correlated. Thus, there …
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Circuit level delay and power analysis of graphene nano-ribbon field-effect transistors using monte carlo simulations and standard cell library characterization
… these devices are very small, the impact of process variation on the circuit’s performance is very large. In this work, we study the impact of process variations on the delay and power of various types of circuits by considering the transistor-level and gate- level impact of the different …
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