Design of on-chip monitoring circuits for clock delay and temperature

As devices continue to scale, Process, Voltage and Temperature (PVT) variations tend to have a bigger impact on circuit performance. The ability to measure this impact provides essential knowledge about the circuit's current performance and opens the door to compensation techniques. Off-chip measurement circuits are usually of limited bandwidth and load the measured circuit, thus affecting the measurement result. Onchip circuits on the other hand have the potential for high bandwidth and, if designed well, have small area and can be incorporated into different parts of the chip. For this project a delay and temperature measurement circuit is designed. The delay measurement circuit relies on a method called Code Density Test (CDT), a statistical method which involves counting the number of asynchronous edges that occur within the relative delay of two synchronous clocks. The temperature measurement circuit converts temperature to a delay which can then be measured by the CDT circuit.

Department dc:contributor.department

Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2016

Author dc:creator

• Kakuru, George Bamuturaki

Advisor dc:contributor.advisor

• Charles G. Sodini, Jeremy Walker, and Andrew Lewine.

• Electrical Engineering and Computer Science.

Statement dc:rights

• M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/105997

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/105997