Iowa State University
A model-based approach to automated test generation and error localization for Simulink/Stateflow
Abstract
dc:description.abstract<p>Simulink/Stateflow is a popular commercial model-based development tool for many industrial domains. For safety and security concerns, verification and testing must be performed on the Simulink/Stateflow designs and the generated code. We present an automatic test generation approach for Simulink/Stateflow based on its translation to a formal model, called Input/Output Extended Finite Automata (I/O-EFA), that is amenable to formal analysis such as test generation. The approach automatically identifies a set of input-output sequences to activate all executable computations in the Simulink/Stateflow diagram by applying three different techniques, model checking, constraint solving and reachability reduction & resolution. These tests (input-output sequences) are then used for validation purposes, and the failed versus passed tests are used to localize the fault to plausible Simulink/Stateflow blocks. The translation and test generation approaches are automated and implemented in a toolbox that can be executed in Matlab that interfaces with NuSMV.</p> <br/> This work has been submitted to a journal for a possible publication. Copyright may be transferred without notice, after which this version may no longer be accessible.
Degree
thesis:*- Name thesis:degree_name
- Doctor of Philosophy
- Level thesis:degree_level
- dissertation
- Discipline thesis:degree_discipline
- Computer Engineering
- Department dc:contributor.department
- Department of Electrical and Computer Engineering
- Year dc:date.issued
- 2013
Author and committee
dc:creator, dc:contributor.*- Author dc:creator
-
- Li, Meng
- Advisor dc:contributor.advisor
-
- Ratnesh Kumar
Rights
- Language dc:language.iso
- en
Identifiers
dc:identifier.*- Identifier
- archive/lib.dr.iastate.edu/etd/16090/
- OAI identifier oai:identifier
- oai:dr.lib.iastate.edu:20.500.12876/30273