{"id":{"repo_id":"iastate","oai_identifier":"oai:dr.lib.iastate.edu:20.500.12876/30273"},"canonical_url":"https://search.dev.ndltd.org/etd/iastate/oai:dr.lib.iastate.edu:20.500.12876/30273","repository":{"repo_id":"iastate","name":"Iowa State University","base_url":"https://dr.lib.iastate.edu/server/oai/request"},"display":{"title":"A model-based approach to automated test generation and error localization for Simulink/Stateflow","abstract":"<p>Simulink/Stateflow is a popular commercial model-based development tool for many industrial domains. For safety and security concerns, verification and testing must be performed on the Simulink/Stateflow designs and the generated code. We present an automatic test generation approach for Simulink/Stateflow based on its translation to a formal model, called Input/Output Extended Finite Automata (I/O-EFA), that is amenable to formal analysis such as test generation. The approach automatically identifies a set of input-output sequences to activate all executable computations in the Simulink/Stateflow diagram by applying three different techniques, model checking, constraint solving and reachability reduction & resolution. These tests (input-output sequences) are then used for validation purposes, and the failed versus passed tests are used to localize the fault to plausible Simulink/Stateflow blocks. The translation and test generation approaches are automated and implemented in a toolbox that can be executed in Matlab that interfaces with NuSMV.</p> <br/> This work has been submitted to a journal for a possible publication. Copyright may be transferred without notice, after which this version may no longer be accessible.","abstract_html":"&lt;p&gt;Simulink/Stateflow is a popular commercial model-based development tool for many industrial domains. For safety and security concerns, verification and testing must be performed on the Simulink/Stateflow designs and the generated code. We present an automatic test generation approach for Simulink/Stateflow based on its translation to a formal model, called Input/Output Extended Finite Automata (I/O-EFA), that is amenable to formal analysis such as test generation. The approach automatically identifies a set of input-output sequences to activate all executable computations in the Simulink/Stateflow diagram by applying three different techniques, model checking, constraint solving and reachability reduction &amp; resolution. These tests (input-output sequences) are then used for validation purposes, and the failed versus passed tests are used to localize the fault to plausible Simulink/Stateflow blocks. The translation and test generation approaches are automated and implemented in a toolbox that can be executed in Matlab that interfaces with NuSMV.&lt;/p&gt; &lt;br/&gt; This work has been submitted to a journal for a possible publication. Copyright may be transferred without notice, after which this version may no longer be accessible.","abstract_has_math":false,"creators":["Li, Meng"],"institution":null,"degree_name":"Doctor of Philosophy","degree_level":"dissertation","degree_discipline":"Computer Engineering","degree_department":"Department of Electrical and Computer Engineering","school":null,"contributors":[],"advisors":["Ratnesh Kumar"],"committee_chairs":[],"committee_members":[],"year":2013,"date_issued":"2013-01-01","date_published":"2013-01-01","updated_at":"2026-07-24T02:38:01Z","subjects":[],"languages":["en"],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier.doi","label":"DOI","values":["https://doi.org/10.31274/etd-180810-5719"],"render_values":[{"text":"https://doi.org/10.31274/etd-180810-5719","href":"https://doi.org/10.31274/etd-180810-5719","code":true}]},{"key":"dc:identifier","label":"Identifier","values":["archive/lib.dr.iastate.edu/etd/16090/"],"render_values":[{"text":"archive/lib.dr.iastate.edu/etd/16090/","href":null,"code":true}]}]},"links":{"outbound_url":"https://dr.lib.iastate.edu/handle/20.500.12876/30273","outbound_label":"Repository record","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Ratnesh Kumar"]},{"key":"dc:contributor.department","label":"Department","values":["Department of Electrical and Computer Engineering"]},{"key":"dc:creator","label":"Author","values":["Li, Meng"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2018-08-11T10:18:14.000"]},{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2020-06-30T03:08:38Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2020-06-30T03:08:38Z"]},{"key":"dc:date.issued","label":"Date","values":["2013-01-01"]},{"key":"dc:type","label":"Dc Type","values":["dissertation"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Computer Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Doctor of Philosophy"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["en"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["archive/lib.dr.iastate.edu/etd/16090/"]},{"key":"dc:identifier.doi","label":"DOI","values":["https://doi.org/10.31274/etd-180810-5719"]},{"key":"dc:identifier.uri","label":"Identifier URI","values":["https://dr.lib.iastate.edu/handle/20.500.12876/30273"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["<p>Simulink/Stateflow is a popular commercial model-based development tool for many industrial domains. For safety and security concerns, verification and testing must be performed on the Simulink/Stateflow designs and the generated code. We present an automatic test generation approach for Simulink/Stateflow based on its translation to a formal model, called Input/Output Extended Finite Automata (I/O-EFA), that is amenable to formal analysis such as test generation. The approach automatically identifies a set of input-output sequences to activate all executable computations in the Simulink/Stateflow diagram by applying three different techniques, model checking, constraint solving and reachability reduction & resolution. These tests (input-output sequences) are then used for validation purposes, and the failed versus passed tests are used to localize the fault to plausible Simulink/Stateflow blocks. The translation and test generation approaches are automated and implemented in a toolbox that can be executed in Matlab that interfaces with NuSMV.</p> <br/> This work has been submitted to a journal for a possible publication. Copyright may be transferred without notice, after which this version may no longer be accessible."]},{"key":"dc:format.mimetype","label":"Dc Format Mimetype","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["A model-based approach to automated test generation and error localization for Simulink/Stateflow"]}]}],"canonical_facts":{"dc:contributor.advisor":["Ratnesh Kumar"],"dc:contributor.department":["Department of Electrical and Computer Engineering"],"dc:creator":["Li, Meng"],"dc:date":["2018-08-11T10:18:14.000"],"dc:date.accessioned":["2020-06-30T03:08:38Z"],"dc:date.available":["2020-06-30T03:08:38Z"],"dc:date.issued":["2013-01-01"],"dc:description.abstract":["<p>Simulink/Stateflow is a popular commercial model-based development tool for many industrial domains. For safety and security concerns, verification and testing must be performed on the Simulink/Stateflow designs and the generated code. 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Copyright may be transferred without notice, after which this version may no longer be accessible."],"dc:format.mimetype":["application/pdf"],"dc:identifier":["archive/lib.dr.iastate.edu/etd/16090/"],"dc:identifier.doi":["https://doi.org/10.31274/etd-180810-5719"],"dc:identifier.uri":["https://dr.lib.iastate.edu/handle/20.500.12876/30273"],"dc:language.iso":["en"],"dc:title":["A model-based approach to automated test generation and error localization for Simulink/Stateflow"],"dc:type":["dissertation"],"thesis:degree_discipline":["Computer Engineering"],"thesis:degree_level":["dissertation"],"thesis:degree_name":["Doctor of Philosophy"]},"updated_at":"2026-07-24T02:38:01Z"}