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Georgia Institute of Technology

Hardware Accelerator Generation Framework for Cryptographic Primitives

Abstract

dc:description.abstract

Cryptographic primitives, consisting of repetitive operations with different inputs, are typically implemented using straight-line C code due to traditional execution on CPUs. Computing these primitives is necessary for secure communication; thus, dedicated hardware accelerators are required in resource and latency-constrained environments. High-Level Synthesis (HLS) generates hardware from high-level implementations in languages like C, enabling the rapid prototyping and evaluation of designs, leading to its prominent use in developing dedicated hardware accelerators. However, directly synthesizing the straight-line C implementations of cryptographic primitives can lead to large hardware designs with excessive resource usage or suboptimal performance. This thesis introduces a tool Cryptonite that automatically generates efficient, synthesizable, and correct-by-design hardware accelerators for cryptographic primitives directly from straight-line C code. Cryptonite first identifies high-level hardware constructs through verified rewriting, emphasizing resource reuse. The second stage automatically explores latency-oriented implementations of the compact design. This enables the flexible scaling of a particular accelerator to meet the hardware requirements. This thesis demonstrates Cryptonite's effectiveness using implementations from the Fiat Cryptography project, a library of verified and auto-generated cryptographic primitives for elliptic-curve cryptography.

Degree

thesis:*
Level thesis:degree_level
Masters
Department dc:contributor.department
Electrical and Computer Engineering
Grantor dc:publisher
Georgia Institute of Technology
Year dc:date.issued
2025

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Sharma M, Karthikeya
Advisor dc:contributor.advisor
  • Hao, Cong (Callie)
Committee members dc:contributor.committeemember
  • Zhang, Qirun
  • Krishna, Tushar

Subjects

dc:subject × 5

Rights

Language dc:language.iso
en_US

Identifiers

dc:identifier.*
Handle dc:identifier.uri
https://hdl.handle.net/1853/77933
OAI identifier oai:identifier
oai:repository.gatech.edu:1853/77933

Chain of custody

source
Harvested from
Georgia Tech
Base URL
repository.gatech.edu/server/oai/request
Last updated
2026-07-27
Source record
OAI-PMH GetRecord
citation

Sharma M, Karthikeya. Hardware Accelerator Generation Framework for Cryptographic Primitives. Masters thesis, Georgia Institute of Technology, 2025. https://hdl.handle.net/1853/77933