Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 41 for “"Hardware accelerator"”.
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Hardware Accelerator Generation Framework for Cryptographic Primitives
… for secure communication; thus, dedicated hardware accelerators are required in resource and latency-constrained environments. High-Level Synthesis (HLS) generates hardware from high-level implementations in languages like C, enabling the rapid prototyping and evaluation of designs, leading …
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Improving the Programmability of A Distributed Hardware Accelerator
… yet they perform poorly on conventional hardware. (Ōmeteōtl, a new hardware accelerator with a distributed-memory and task-based execution model, aims to address these performance bottlenecks. However, programming for (Ōmeteōtl is low-level, error-prone, and far removed from the …
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Functional and timing models for a programmable hardware accelerator
… memory accesses. A proposed programmable hardware accelerator using a spatial architecture paired with triggered instructions could solve this class of problems more efficiently. Performance models are useful for evaluating the performance of different applications and design alternatives. …
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Designing a Programmable Hardware Accelerator for Fully Homomorphic Encryption
… adoption. We present F1, the first FHE accelerator that is programmable, i.e., capable of executing full FHE programs. F1 builds on an in-depth architectural analysis of the characteristics of FHE computations that reveals acceleration opportunities. F1 is a wide-vector processor with …
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Robust and reliable hardware accelerator design through high-level synthesis
… in the integration of a wide variety of complex hardware accelerators in SoCs. Thus the challenge is to design complex, custom hardware that is efficient, but also correct and reliable. High-level synthesis shows promise to address the problem of complex hardware design by providing a bridge from …
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OnionChopper: A Modular Arithmetic Hardware Accelerator for Private Information Retrieval
… a small, fast, and energy efficient hardware accelerator on which to offload the heaviest computational work. This hardwareaccelerator is optimized for astate-of-the-art PIRalgorithm, Onion- PIR, but is widely applicable due to similarities in the fundamental algorithms and …
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Tardigrade: A Hardware Accelerator for Sparse Matrix Multiplication and Sparse Convolution
… and deep learning. Prior work has proposed accelerators for each of these primitives, but these systems are often specialized to run either SpMSpM or sparse convolution efficiently. Although there are methods to run sparse convolution on an SpMSpM accelerator, and vice versa, this typically …
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Application Specific Domain Co-design Hardware Accelerator IP for Deep Learning Enabled Internet-of-Things
L'abstract è presente nell'allegato / the abstract is in the attachment
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Energy-Efficient Real-Time Hardware Acceleration for Gaussian Fitting
… of an FPGA (Field Programmable Gate Array)-based hardware accelerator that enables Gaussian fitting based on the SPGF algorithm with 10.4× lower energy per image (based on post-implementation power analysis), compared to the original, software implementation. By using fixed-point numerical …
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FPGA-based hardware acceleration for a key-value store database
… database performance is the use of dedicated hardware to effectively complement or replace software to 'accelerate' the overall system. This thesis investigates the use of a Field-Programmable Gate Array (FPGA) as a hardware accelerator for a key-value database. Utilized as a platform of …
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Energy Efficient Hardware Accelerators for Packet Classification and String Matching
… algorithms and energy efficient high throughput hardware accelerators that implement packet classification and fixed string matching. These computationally heavy and memory intensive tasks are used by networking equipment to inspect all packets at wire speed. The constant growth in Internet usage …
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Puppetmaster: a certified hardware architecture for task parallelism
This thesis presents Puppetmaster, a hardware accelerator for transactional workloads. Existing software and hardware frameworks for transactional memory and online transaction processing are not able to scale to hundreds or thousands of cores unless the rate of conflicts between transactions is …
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Hardware acceleration for sparse Fourier image reconstruction
… In this paper we present an RC-based hardware accelerator for an important medical imaging algorithm: iterative sparse Fourier image reconstruction. We transform the algorithm to exploit massive parallelism available in the FPGA fabric. Our design allows different ways of chaining …
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On The Parallelization Of Integer Polynomial Multiplication
With the advent of hardware accelerator technologies, multi-core processors and GPUs, much effort for taking advantage of those architectures by designing parallel algorithms has been made. To achieve this goal, one needs to consider both algebraic complexity and parallelism, plus making efficient …
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Haptic Interaction with 3D oriented point clouds on the GPU
… for Haptic Interaction using the GPU as a hardware accelerator, and includes an approach for enabling the modi�cation of data during interaction. The results demonstrate the limits and capabilities of these techniques in the context of volume rendering for haptic applications. Also, the use …
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A Deep Learning and Signal Processing Architecture Using Frequency-Encoded RF Photonics
… efforts have been made to create custom hardware to accelerate deep neural network training and inference. Among these efforts are optical neural networks, which have been a promising approach that excel at linear operations but struggle with nonlinear implementations. Here, we propose …
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Enhancing GNU Radio for Hardware Accelerated Radio Design
… create flexible radio designs. In terms of hardware, the maturity of FPGAs give radio designers new opportunities to develop high-speed radios having high-throughput and low-latency, yet the conventional build-time for FPGAs is a limiting factor for productivity. Recent research has lead to …
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Automated communication and floorplan-aware hardware/software co-design for SoC
… engineering task due to the vast design space of hardware accelerators and HW/SW task partitioning. Depending on the partitioning decision, communication between parts of the SoC must be also optimized such that the overall runtime including both computation and communication would be fast. In …
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Learning from minimally labeled data with accelerated convolutional neural networks
… an optimized streaming method for ConvNets’ hardware accelerator on an embedded platform. It is tested on object classification and detection applications using ConvNets. Experimental results indicate high computational efficiency, and significant performance upgrades over all other existing …
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FPGA-Roofline: An Insightful Model for FGPA-based Hardware Acceleration in Modern Embedded Systems
… applications. This trend has led to emergence of hardware accelerators in embedded systems. While the processing power of dedicated hardware modules seems appealing, they require significant effort of development and integration to gain performance benefit. Thus, it is prudent to investigate and …
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