Circuit and algorithm design to enable edge intelligence

“Edge Intelligence” (EI) is a promising alternative to a centralized could-IoT paradigm that has inherent advantages with communication cost, processing latency, data security, network robustness, and so on. However, EI Design is essentially challenging to support ever-demanding artificial intelligence on resource-constrained devices with a slowly-evolving technology node. Moreover, as an emerging field, a systematic investigation is required to facilitate future EI research. This work tends to provide such a comprehensive study on circuit and algorithm solutions for edge intelligence. First, a state-of-art EI overview will be presented along with the proposed EI design landscape, EI evaluation figure-of-merit, and generic EI design methodology. Then, the proposed EI scheme will be elaborated on three sub-topics: EI computation, EI system integration, and distributed EI. Within each sub-topic, a detailed EI platform will be discussed as an example work to illustrate EI design considerations, solutions space, and application scenarios. Finally, conclusions will be drawn to address current and future EI research challenges/opportunities.

Level thesis:degree_level

Doctoral

Department dc:contributor.department

Electrical and Computer Engineering

Grantor dc:publisher

Georgia Institute of Technology

Year dc:date.issued

2020

Author dc:creator

• Cao, Ningyuan

Advisor dc:contributor.advisor

• Raychowdhury, Arijit

Committee members dc:contributor.committeemember

• Lim, Sung-kyu
• Swaminathan, Madhavan
• Bakir, Muhannad S.
• Sen, Shreyas

• Edge intelligence
• Edge computation
• Internet-of-things
• System-on-chip
• ASIC
• Low-power circuit
• Machine learning
• Artificial intelligence
• Micro-robotics

Language dc:language.iso

en_US

Handle dc:identifier.uri

http://hdl.handle.net/1853/63653

OAI identifier oai:identifier

oai:repository.gatech.edu:1853/63653