Intelligent cache management for heterogeneous memory systems

DRAM caches are important for enabling effective heterogeneous memory systems that can transparently provide the bandwidth of high-bandwidth memories and the capacity of high-capacity memories. This dissertation investigates enabling intelligent cache management for tag-inside-cacheline DRAM cache designs. Such a DRAM cache uses a direct-mapped design, co-locates the tag and data within the DRAM array, and streams out the tag and the data concurrently on an access. The direct-mapped design has been shown to be effective for enabling low latency and bandwidth-efficient tag access. However, such a direct-mapped design can have lower hit-rate and high bandwidth cost to confirm misses. This dissertation investigates simple architectural techniques to improve the hit-rate and bandwidth consumption of such DRAM caches by enabling associativity, replacement policies, and reduced miss probes at low bandwidth cost to improve the performance of heterogeneous memory systems.

Level thesis:degree_level

Doctoral

Department dc:contributor.department

Electrical and Computer Engineering

Grantor dc:publisher

Georgia Institute of Technology

Year dc:date.issued

2019

Author dc:creator

• Young, Vinson

Advisor dc:contributor.advisor

• Qureshi, Moinuddin K.

Committee members dc:contributor.committeemember

• Kim, Hyesoon
• Jaleel, Aamer
• Prvulovic, Milos

• Non-volatile memory
• 3D-XPoint
• Stacked DRAM
• HBM
• Hybrid memory
• DRAM cache
• Associativity
• Compression
• Way prediction
• Replacement policy

Language dc:language.iso

en_US

Handle dc:identifier.uri

http://hdl.handle.net/1853/61710

OAI identifier oai:identifier

oai:repository.gatech.edu:1853/61710