{"id":{"repo_id":"gatech","oai_identifier":"oai:repository.gatech.edu:1853/61710"},"canonical_url":"https://search.dev.ndltd.org/etd/gatech/oai:repository.gatech.edu:1853/61710","repository":{"repo_id":"gatech","name":"Georgia Tech","base_url":"https://repository.gatech.edu/server/oai/request"},"display":{"title":"Intelligent cache management for heterogeneous memory systems","abstract":"DRAM caches are important for enabling effective heterogeneous memory systems that can transparently provide the bandwidth of high-bandwidth memories and the capacity of high-capacity memories. This dissertation investigates enabling intelligent cache management for tag-inside-cacheline DRAM cache designs. Such a DRAM cache uses a direct-mapped design, co-locates the tag and data within the DRAM array, and streams out the tag and the data concurrently on an access. The direct-mapped design has been shown to be effective for enabling low latency and bandwidth-efficient tag access. However, such a direct-mapped design can have lower hit-rate and high bandwidth cost to confirm misses. This dissertation investigates simple architectural techniques to improve the hit-rate and bandwidth consumption of such DRAM caches by enabling associativity, replacement policies, and reduced miss probes at low bandwidth cost to improve the performance of heterogeneous memory systems.","abstract_html":"DRAM caches are important for enabling effective heterogeneous memory systems that can transparently provide the bandwidth of high-bandwidth memories and the capacity of high-capacity memories. This dissertation investigates enabling intelligent cache management for tag-inside-cacheline DRAM cache designs. Such a DRAM cache uses a direct-mapped design, co-locates the tag and data within the DRAM array, and streams out the tag and the data concurrently on an access. The direct-mapped design has been shown to be effective for enabling low latency and bandwidth-efficient tag access. However, such a direct-mapped design can have lower hit-rate and high bandwidth cost to confirm misses. This dissertation investigates simple architectural techniques to improve the hit-rate and bandwidth consumption of such DRAM caches by enabling associativity, replacement policies, and reduced miss probes at low bandwidth cost to improve the performance of heterogeneous memory systems.","abstract_has_math":false,"creators":["Young, Vinson"],"institution":"Georgia Institute of Technology","degree_name":null,"degree_level":"Doctoral","degree_discipline":null,"degree_department":"Electrical and Computer Engineering","school":null,"contributors":[],"advisors":["Qureshi, Moinuddin K."],"committee_chairs":[],"committee_members":["Kim, Hyesoon","Jaleel, Aamer","Prvulovic, Milos"],"year":2019,"date_issued":"2019-05-21","date_published":"2019-05-21","updated_at":"2026-07-27T19:50:47Z","subjects":["Non-volatile memory","3D-XPoint","Stacked DRAM","HBM","Hybrid memory","DRAM cache","Associativity","Compression","Way prediction","Replacement policy"],"languages":["en_US"],"rights":[],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/1853/61710","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Qureshi, Moinuddin K."]},{"key":"dc:contributor.committeemember","label":"Committee Member","values":["Kim, Hyesoon","Jaleel, Aamer","Prvulovic, Milos"]},{"key":"dc:contributor.department","label":"Department","values":["Electrical and Computer Engineering"]},{"key":"dc:creator","label":"Author","values":["Young, Vinson"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2019-08-21T13:51:32Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2019-08-21T13:51:32Z"]},{"key":"dc:date.issued","label":"Date","values":["2019-05-21"]},{"key":"dc:publisher","label":"Institution","values":["Georgia Institute of Technology"]},{"key":"dc:type","label":"Dc Type","values":["Text"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Doctoral"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Non-volatile memory","3D-XPoint","Stacked DRAM","HBM","Hybrid memory","DRAM cache","Associativity","Compression","Way prediction","Replacement policy"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["en_US"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/1853/61710"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["DRAM caches are important for enabling effective heterogeneous memory systems that can transparently provide the bandwidth of high-bandwidth memories and the capacity of high-capacity memories. This dissertation investigates enabling intelligent cache management for tag-inside-cacheline DRAM cache designs. Such a DRAM cache uses a direct-mapped design, co-locates the tag and data within the DRAM array, and streams out the tag and the data concurrently on an access. The direct-mapped design has been shown to be effective for enabling low latency and bandwidth-efficient tag access. However, such a direct-mapped design can have lower hit-rate and high bandwidth cost to confirm misses. This dissertation investigates simple architectural techniques to improve the hit-rate and bandwidth consumption of such DRAM caches by enabling associativity, replacement policies, and reduced miss probes at low bandwidth cost to improve the performance of heterogeneous memory systems."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["Ph.D."]},{"key":"dc:format.mimetype","label":"Dc Format Mimetype","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Intelligent cache management for heterogeneous memory systems"]}]}],"canonical_facts":{"dc:contributor.advisor":["Qureshi, Moinuddin K."],"dc:contributor.committeemember":["Kim, Hyesoon","Jaleel, Aamer","Prvulovic, Milos"],"dc:contributor.department":["Electrical and Computer Engineering"],"dc:creator":["Young, Vinson"],"dc:date.accessioned":["2019-08-21T13:51:32Z"],"dc:date.available":["2019-08-21T13:51:32Z"],"dc:date.issued":["2019-05-21"],"dc:description.abstract":["DRAM caches are important for enabling effective heterogeneous memory systems that can transparently provide the bandwidth of high-bandwidth memories and the capacity of high-capacity memories. This dissertation investigates enabling intelligent cache management for tag-inside-cacheline DRAM cache designs. Such a DRAM cache uses a direct-mapped design, co-locates the tag and data within the DRAM array, and streams out the tag and the data concurrently on an access. The direct-mapped design has been shown to be effective for enabling low latency and bandwidth-efficient tag access. However, such a direct-mapped design can have lower hit-rate and high bandwidth cost to confirm misses. This dissertation investigates simple architectural techniques to improve the hit-rate and bandwidth consumption of such DRAM caches by enabling associativity, replacement policies, and reduced miss probes at low bandwidth cost to improve the performance of heterogeneous memory systems."],"dc:description.degree":["Ph.D."],"dc:format.mimetype":["application/pdf"],"dc:identifier.uri":["http://hdl.handle.net/1853/61710"],"dc:language.iso":["en_US"],"dc:publisher":["Georgia Institute of Technology"],"dc:subject":["Non-volatile memory","3D-XPoint","Stacked DRAM","HBM","Hybrid memory","DRAM cache","Associativity","Compression","Way prediction","Replacement policy"],"dc:title":["Intelligent cache management for heterogeneous memory systems"],"dc:type":["Text"],"thesis:degree_level":["Doctoral"]},"updated_at":"2026-07-27T19:50:47Z"}