Novel Power Semiconductor Devices and Technologies

This thesis is devoted towards the development of efficient power semiconductor devices. It will focus upon the development of 1200V and 1700V fast recovery diodes and two MOS gated thyristor structures viz. the Accumulation Layer enhanced Emitter Switched Thyristor (ALEST) and the Clustered IGBT (CIGBT). Furthermore the insight into the principles of operation and modern optimisation techniques of fast recover diodes, IGBT’s and MOS gated thyristors are also considered. 1200V and 1700V fast recovery diodes are developed employing the same novel p+ offset edge termination technique. The 1200V devices show a hot/cold leakage current and forward voltage drop of 518pA/L42|iA and 3.19V/2.99V at 400K and room temperature respectively whereas the 1700V devices show a hot/cold leakage current and forward voltage drop of 1.58mA/2.95|.iA and 3.01 V/2.82V respectively. In terms of switching, the switching waveforms remain soft whilst switching at lOOOA/ps with a stray inductance of 150pH both at a case temperature of 300K and 400K. Bench marking of these components to commercially available 1200V and 1700V devices shows improved reverse recovery characteristic for the 1200V component whereas the 1700V structure shows a 21% and 76% improvement in the room temperature forward voltage drop and reverse recovery charge respectively. For the ALEST, simulation results investigate the influence of the implantation dose of the n/p well layers and the accumulation region upon the device performance. This shows that the final concentration of the p well, which is the resultant of the initial p well implantation dose and the compensation of the n well is critical to the device performance. If the p well dose is too low breakdown is compromised whereas a low n well concentration results in a high forward voltage drop. The accumulation layer is shown to enhance the on-state and switching performance as the injection efficiency of the NPN transistor is controlled by the gate voltage. Simulations comparing the ALEST to an IGBT and EST structures optimised to the same process flow show considerable improvements in terms of switching losses when the same forward voltage drop is considered. 2kV DMOS ALEST devices are demonstrated and the influence of the n well length and concentration is evaluated. Experimental results show that due to the thyristor mode of operation, the ALEST displays improvements in forward voltage drop when compared to IGBT structures fabricated with the same processing sequence. These show that the n well concentration and length influences the on-state performance by increasing the carrier injection into the n- drift region and reducing the break-over voltage prior to thyristor latch-up. A second MOS gated thyristor structure called the Clustered IGBT is evaluated. This structure employs a capacitive coupled tum-on mechanism which eliminates snapback from the tum-on process. The device also incorporates a unique self-clamping feature which aids current saturation at high gate voltages, improves the safe operating area, and protects the gate structures and cathode cells from high voltage. This self-clamping feature in analysed in detail with respect to n well dose, lifetime and temperature showing that it is weakly dependant upon carrier lifetime and temperature and strongly dependant upon the n well dose. Finally the performance of an optimised 3kV CIGBT is compared to an IGBT. These results show that the CIGBT displays a 40% reduction in switching losses when a 3V forward voltage drop is considered.

Name dc:type.qualificationname

PhD

Level dc:type.qualificationlevel

Doctoral

Grantor dc:publisher.institution

De Montfort University

Year dc:date.issued

2003

Author dc:creator

• Sweet, Mark Robert

Licence

• https://dora.dmu.ac.uk/bitstreams/9245741b-0bb2-4c4f-bfe1-5ebe32924bab/download