Efficient and Verifiable Timing Channel Protection for Multi-Core Processors

Modern computing systems are becoming increasingly vulnerable to timing channel attacks that leak confidential information through the timing of microarchitectural events. Many timing channel attacks are caused by the interference between different programs in the shared resources of a multi-core processor. For example, an attacker program's cache lines can be evicted by a victim program, which allows the attacker to infer secret information about the victim. Timing channel attacks pose serious threats to contemporary computing systems because they can bypass traditional defense mechanisms such as access control. Previous studies have even demonstrated a practical timing channel attack to recover the keystrokes of a user in the commercial Amazon EC2 cloud. In this thesis, we explored new timing channel attacks and developed timing channel protection schemes for some of the hardware resources in a multi-core processor. Specifically, we discovered new timing channel attacks in the shared on-chip networks and memory controllers. We proposed multiple protection mechanisms for on-chip networks, caches and memory controllers. Our protection schemes cover three high-level approaches: bi-directional protections, uni-directional protections and protections that trade off security for performance. We evaluate our protection schemes and show that the proposed schemes are effective against timing channel attacks while achieving performance improvements over previous protection schemes. Finally, we implemented some of the protection mechanisms in RTL and used SecVerilog to verify the information flow control in hardware. The results show that the protection mechanisms indeed remove timing channels at the gate level.

Name thesis:degree_name

Ph. D., Electrical and Computer Engineering

Level thesis:degree_level

Doctor of Philosophy

Discipline thesis:degree_discipline

Electrical and Computer Engineering

Grantor

Cornell University

Year dc:date.issued

2017

Author dc:creator

• Wang, Yao

Committee members dc:contributor.committeemember

• Myers, Andrew C.
• Batten, Christopher

• Computer engineering
• Computer science
• Computer Architecture
• Memory Controller
• Security
• SecVerilog
• Timing Channel
• cache

Language dc:language.iso

en_US

DOI

https://doi.org/10.7298/X49K487W

Dc Identifier Other

ProQuest Submission ID: 10146
ProQuest Publication ID: 10253735

OAI identifier oai:identifier

oai:ecommons.cornell.edu:1813/47878