Mixed signal compensation of sampling errors in ADCs due to noisy DPLL clock sources

This thesis clarifies a method to compensate for sampling errors in ADCs when a noisy digital phase locked-loop (DPLL). A time domain DPLL is built by MATLAB Simulink with a phase noise model. The phase noise is obtained from a measured oscillator. When DPLL achieve lock, the time-to-digital converter (TDC) provides an estimate of jitter which is used with an analog differentiator to provide an estimate of the ADC sampling error. This correction scheme has reduced the side band noise in the output signal and allows the ADC effective number of bits at high frequency to be improved from 2 bits to 6 bits. When slope and double slope ADCs with 6 bits of resolution are selected the scheme can be implemented consuming up to additional power consumption of 6.8mW.

Grantor dc:publisher

University College Cork

Year dc:date.issued

2021

Author dc:creator

• Zheng, Hao

Advisors dc:contributor.advisor

• O'Hare, Daniel
• O'Connell, Ivan

• Mixed signal compensation
• DPLL clock sources
• Sampling errors in ADCs

Statement dc:rights

• © 2021, Hao Zheng.

Licence dc:rights.uri

• https://creativecommons.org/licenses/by-sa/4.0/

Language dc:language.iso

en

Handle dc:identifier.uri

https://hdl.handle.net/10468/12483

OAI identifier oai:identifier

oai:cora.ucc.ie:10468/12483