{"id":{"repo_id":"cork","oai_identifier":"oai:cora.ucc.ie:10468/12483"},"canonical_url":"https://search.dev.ndltd.org/etd/cork/oai:cora.ucc.ie:10468/12483","repository":{"repo_id":"cork","name":"University College Cork","base_url":"https://cora.ucc.ie/server/oai/request"},"display":{"title":"Mixed signal compensation of sampling errors in ADCs due to noisy DPLL clock sources","abstract":"This thesis clarifies a method to compensate for sampling errors in ADCs when a noisy digital phase locked-loop (DPLL). A time domain DPLL is built by MATLAB Simulink with a phase noise model. The phase noise is obtained from a measured oscillator. When DPLL achieve lock, the time-to-digital converter (TDC) provides an estimate of jitter which is used with an analog differentiator to provide an estimate of the ADC sampling error. This correction scheme has reduced the side band noise in the output signal and allows the ADC effective number of bits at high frequency to be improved from 2 bits to 6 bits. When slope and double slope ADCs with 6 bits of resolution are selected the scheme can be implemented consuming up to additional power consumption of 6.8mW.","abstract_html":"This thesis clarifies a method to compensate for sampling errors in ADCs when a noisy digital phase locked-loop (DPLL). A time domain DPLL is built by MATLAB Simulink with a phase noise model. The phase noise is obtained from a measured oscillator. When DPLL achieve lock, the time-to-digital converter (TDC) provides an estimate of jitter which is used with an analog differentiator to provide an estimate of the ADC sampling error. This correction scheme has reduced the side band noise in the output signal and allows the ADC effective number of bits at high frequency to be improved from 2 bits to 6 bits. When slope and double slope ADCs with 6 bits of resolution are selected the scheme can be implemented consuming up to additional power consumption of 6.8mW.","abstract_has_math":false,"creators":["Zheng, Hao"],"institution":"University College Cork","degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":null,"school":null,"contributors":[],"advisors":["O'Hare, Daniel","O'Connell, Ivan"],"committee_chairs":[],"committee_members":[],"year":2021,"date_issued":"2021-06","date_published":"2021-06","updated_at":"2026-07-24T01:48:42Z","subjects":["Mixed signal compensation","DPLL clock sources","Sampling errors in ADCs"],"languages":["en"],"rights":["© 2021, Hao Zheng."],"rights_urls":["https://creativecommons.org/licenses/by-sa/4.0/"],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/10468/12483","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["O'Hare, Daniel","O'Connell, Ivan"]},{"key":"dc:creator","label":"Author","values":["Zheng, Hao"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2022-01-26T15:35:50Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2022-01-26T15:35:50Z"]},{"key":"dc:date.issued","label":"Date","values":["2021-06"]},{"key":"dc:publisher","label":"Institution","values":["University College Cork"]},{"key":"dc:type","label":"Dc Type","values":["Masters thesis (Research)"]},{"key":"dc:type.qualificationlevel","label":"Dc Type Qualificationlevel","values":["Masters"]},{"key":"dc:type.qualificationname","label":"Dc Type Qualificationname","values":["MRes - Master of Research"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Mixed signal compensation","DPLL clock sources","Sampling errors in ADCs"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["© 2021, Hao Zheng."]},{"key":"dc:rights.uri","label":"Rights URI","values":["https://creativecommons.org/licenses/by-sa/4.0/"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["https://hdl.handle.net/10468/12483"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["This thesis clarifies a method to compensate for sampling errors in ADCs when a noisy digital phase locked-loop (DPLL). A time domain DPLL is built by MATLAB Simulink with a phase noise model. The phase noise is obtained from a measured oscillator. When DPLL achieve lock, the time-to-digital converter (TDC) provides an estimate of jitter which is used with an analog differentiator to provide an estimate of the ADC sampling error. This correction scheme has reduced the side band noise in the output signal and allows the ADC effective number of bits at high frequency to be improved from 2 bits to 6 bits. When slope and double slope ADCs with 6 bits of resolution are selected the scheme can be implemented consuming up to additional power consumption of 6.8mW."]},{"key":"dc:format.mimetype","label":"Dc Format Mimetype","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Mixed signal compensation of sampling errors in ADCs due to noisy DPLL clock sources"]}]}],"canonical_facts":{"dc:contributor.advisor":["O'Hare, Daniel","O'Connell, Ivan"],"dc:creator":["Zheng, Hao"],"dc:date.accessioned":["2022-01-26T15:35:50Z"],"dc:date.available":["2022-01-26T15:35:50Z"],"dc:date.issued":["2021-06"],"dc:description.abstract":["This thesis clarifies a method to compensate for sampling errors in ADCs when a noisy digital phase locked-loop (DPLL). A time domain DPLL is built by MATLAB Simulink with a phase noise model. The phase noise is obtained from a measured oscillator. When DPLL achieve lock, the time-to-digital converter (TDC) provides an estimate of jitter which is used with an analog differentiator to provide an estimate of the ADC sampling error. This correction scheme has reduced the side band noise in the output signal and allows the ADC effective number of bits at high frequency to be improved from 2 bits to 6 bits. When slope and double slope ADCs with 6 bits of resolution are selected the scheme can be implemented consuming up to additional power consumption of 6.8mW."],"dc:format.mimetype":["application/pdf"],"dc:identifier.uri":["https://hdl.handle.net/10468/12483"],"dc:language.iso":["en"],"dc:publisher":["University College Cork"],"dc:rights":["© 2021, Hao Zheng."],"dc:rights.uri":["https://creativecommons.org/licenses/by-sa/4.0/"],"dc:subject":["Mixed signal compensation","DPLL clock sources","Sampling errors in ADCs"],"dc:title":["Mixed signal compensation of sampling errors in ADCs due to noisy DPLL clock sources"],"dc:type":["Masters thesis (Research)"],"dc:type.qualificationlevel":["Masters"],"dc:type.qualificationname":["MRes - Master of Research"]},"updated_at":"2026-07-24T01:48:42Z"}