4H-SiC FinFET devices and modelling

As a semiconductor material, Silicon Carbide (SiC) has promising electrical properties in high-voltage, high-frequency switching applications for various power electronics applications. In particular, SiC power MOSFETs have undergone remarkable development and optimisation, turning them into serious competitors to more conventional Si unipolar and bipolar power devices across a wide range of voltage ratings. Nevertheless, the widespread adoption of conventional SiC MOSFETs remains hampered by the poor quality of the SiC/SiO2 interface, resulting in extremely low electron mobility in the inversion layer (∼5cm2/(Vs)). Various novel processing techniques have been developed to address this issue, such as POCI3 annealing at 1000 ◦C, which increases mobility close to or even above 100cm2/(Vs) on the (0001)-face. Despite the challenges of integrating these processing methods into practical production environments, the electron mobility of 4H-SiC in the channel region remains significantly lower compared to both silicon (over ∼1000cm2/(Vs)) and GaN (∼1700cm2/(Vs) for the two-dimensional electron gas, 2DEG). As a result, SiC devices are expected to dominate applications at 1kV and above, where channel resistance is no longer the primary limiting factor in power devices. From this perspective, many engineers are focusing on developing advanced features for higher voltage ratings with significant improvements in device performance. In this work, the individual impact of scattering mechanisms on electron mobility in the inversion layer has been comprehensively studied using TCAD simulations. Based on these results, it is demonstrated that electron mobility can be significantly enhanced using the ultra-narrow-body fin concept (the FinFET effect) in device structure design. The feasibility of integrating the fin structure into practical devices is investigated and compared to conventional designs, revealing that the fin design not only enhances device performance by improving electron mobility but also provides threshold voltage stability at elevated temperatures, along with other inherent advantages. However, a significant reduction in the threshold voltage has also been observed in practical devices with a fin structure. To address this issue,this study proposes an advanced design strategy to control the threshold voltage in MOS devices while preserving the improvements in channel mobility.

Name dc:type.qualificationname

Doctor of Philosophy (PhD)

Level dc:type.qualificationlevel

Doctoral

Grantor dc:publisher.institution

University of Cambridge

Year dc:date.issued

2025

Author dc:creator

• Wang, Qian

Advisor dc:contributor.advisor

• Udrea, Florin

• FinFET
• SiC

Licence

• https://www.repository.cam.ac.uk/bitstreams/f0063c3a-a2f7-460a-935f-f076342588eb/download
• http://purl.org/NET/rdflicense/allrightsreserved

Language dc:language

eng

Author Identifier

0009-0008-9141-7253

OAI identifier oai:identifier

oai:www.repository.cam.ac.uk:1810/390528