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Showing 1 to 20 of 44 for “"FinFET"”.

  1. Study of subthreshold behavior of FinFet

    … digital circuits. Fin Field Effect Transistor (FinFET) is considered to be an alternate MOSFET structure in the deep sub-micron regime. A 3D Poisson equation solver is employed to study the subthreshold behavior of FinFET. Based on potential distribution inside the fin, the appropriate band …

    unlv Repository record for Study of subthreshold behavior of FinFet (opens in a new tab)

  2. 4H-SiC FinFET devices and modelling

    … using the ultra-narrow-body fin concept (the FinFET effect) in device structure design. The feasibility of integrating the fin structure into practical devices is investigated and compared to conventional designs, revealing that the fin design not only enhances device performance by improving …

    cambridge Repository record for 4H-SiC FinFET devices and modelling (opens in a new tab)

  3. Optically Controlled Vertical GaN finFET for Power Applications

    … of an optically controlled vertical GaN finFET. The first part of the thesis describes the physics and design of the device assisted by simulation, followed by the fabrication using a Design-Technology Co-Optimization (DTCO) approach. Finally, device measurements are presented. Our …

    mit Repository record for Optically Controlled Vertical GaN finFET for Power Applications (opens in a new tab)

  4. Static random-access memory designs based on different FinFET at lower technology node (7nm)

    … effects (SCE) of conventional CMOS. FinFET devices are promising emerging devices that can be utilized to improve the performance of SRAM designs at lower technology nodes. In this thesis, I present detail analysis of SRAM cells using different types of FinFET devices at 7nm …

    umkc Repository record for Static random-access memory designs based on different FinFET at lower technology node (7nm) (opens in a new tab)

  5. Gate-Oxide-Short Defect Analysis and Fault Modeling Based on FinFET's 3D Structure

    FinFET is one of the most promising candidates in replacing planar MOSFET beyond the 22nm technology node due to further improvements in the transistor performance. However, the complexity of FinFET manufacturing process due to its three-dimensional structure and reduced critical dimensions have …

    carleton Repository record for Gate-Oxide-Short Defect Analysis and Fault Modeling Based on FinFET's 3D Structure (opens in a new tab)

  6. ESD robustness of stacked NMOS transistors for high-voltage tolerant output drivers in FinFET technology

    Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2027-05-01

    uiuc Repository record for ESD robustness of stacked NMOS transistors for high-voltage tolerant output drivers in FinFET technology (opens in a new tab)

  7. A 2-D Scalable Third harmonic radiator at 291.3 GHz with -2 dBm of Radiated Power in 22 nm FinFET Technology

    … proposed radiator is implemented on Intel 22 nm FinFET (FFL) technology, which enables high-performance high-speed circuits. The presented radiator is an addition to the state-of-the-art radiators and combines several advantages of previous designs.

    mit Repository record for A 2-D Scalable Third harmonic radiator at 291.3 GHz with -2 dBm of Radiated Power in 22 nm FinFET Technology (opens in a new tab)

  8. Monte Carlo simulation for high-frequency intrinsic noise analysis of MOSFET

    … into noise two-port model. A 30 nm double gate FinFET is chosen as a simulation model and the intrinsic noise of the device is examined. As a result, the double gate FinFET showed lower gate and source access resistance, and minimum noise figure, which contains important information about the …

    uiuc Repository record for Monte Carlo simulation for high-frequency intrinsic noise analysis of MOSFET (opens in a new tab)

  9. Modelling and enhancement of the channel mobility of 4H-SiC power MOS devices

    … values, thereby effectively yielding a SiC FinFET. The feasibility of applying the FinFET topology to practical power devices is subsequently investigated by studying the all-round performances of two different vertical power FinFET designs and comparing them with those of next generation …

    cambridge Repository record for Modelling and enhancement of the channel mobility of 4H-SiC power MOS devices (opens in a new tab)

  10. Development of vertical bulk gallium nitride power devices

    … fabrication technologies for vertical power FinFETs. Key processing stesps are refined and demonstrated on large-area devices. The final topic covered is GaN superjunction (SJ) technology in the context vertical power FinFETs. The SJ FinFET concept is first introduced then an underutilized …

    mit Repository record for Development of vertical bulk gallium nitride power devices (opens in a new tab)

  11. Nanoscale Nonvolatile Memory Circuit Design using Emerging Spin Transfer Torque Magnetic Random Access Memory

    … of Access transistor is needed. We are using FinFET as access transistor in the STT-MRAM bit cell. FinFET based bit cell is designed to get an advantage of scaling down. Analysis is done and proven that the power consumption, standalone leakage current is less when compared to NMOS based …

    umkc Repository record for Nanoscale Nonvolatile Memory Circuit Design using Emerging Spin Transfer Torque Magnetic Random Access Memory (opens in a new tab)

  12. Vertical gallium nitride power devices on bulk native substrates

    … of the thesis presents a novel vertical power FinFET design with only n-GaN epi-layers. One of the key fabrication processes required for this device structure is to achieve a smooth vertical fin sidewall by combining dry/wet etch. The normally-off power FinFET demonstrates excellent …

    mit Repository record for Vertical gallium nitride power devices on bulk native substrates (opens in a new tab)

  13. Multigate MOSFETs for digital performance and high linearity, and their fabrication techniques

    … for 3D fin channel formation. InP junctionless FinFETs with record high-aspect-ratio (~ 50:1) fins are demonstrated by this method for the first time. The i-MacEtch process flow eliminates dry-etching-induced plasma damage, high energy ion implantation damage, and high temperature annealing, …

    uiuc Repository record for Multigate MOSFETs for digital performance and high linearity, and their fabrication techniques (opens in a new tab)

  14. Performance variations due to layout-dependent stress in VLSI circuits

    … are used to enhance transistor performance. In FinFET technologies, these stressors lose their effectiveness with reducing contacted gate pitch. Moreover, owing to the three dimensional nature of the FinFETs, the beneficial stress relaxes along the free-edges of standard cell layouts. Thus, the …

    umn Repository record for Performance variations due to layout-dependent stress in VLSI circuits (opens in a new tab)

  15. Statistical modeling and simulation of variability and reliability of CMOS technology

    … be considered simultaneously. In addition, the FinFET architecture can cause additional degradation of the transistors. The field-crowding and 2D-hydrogen diffusion at the fin corners can make the reliability assessment more complicated compared to the planar counterpart. We also proposed a …

    purdue-thes Repository record for Statistical modeling and simulation of variability and reliability of CMOS technology (opens in a new tab)

  16. Design, Modeling and Analysis of Non-classical Field Effect Transistors

    … (SOI) and body-on-insulator (BOI) FinFETs are simulated to demonstrate their impact on the performance of volatile memory SRAM module with consideration of self-heating effects. Comprehensive simulation results suggest that the current drivability degradation due to increased device …

    syracuse-diss Repository record for Design, Modeling and Analysis of Non-classical Field Effect Transistors (opens in a new tab)

  17. TCAD approaches to multidimensional simulation of advanced semiconductor devices

    … (RD). The impact of such phenomena on FinFET devices, which represent a promising alternative to planar CMOS technology, is estimated through 2D and 3D TCAD simulations and statistical tools, taking into account matching performance of single devices as well as basic circuit blocks such …

    bologna Repository record for TCAD approaches to multidimensional simulation of advanced semiconductor devices (opens in a new tab)

  18. Monte Carlo Simulation of Nanostructures: Semiconductor Devices to Ion Channels

    … the validity of the model. Device simulations of finFET devices show that quantum effects do not have significant effect on device currents. Furthermore, the presence of long fin extension regions can significantly downgrade the performance of finFET devices. The effects of dielectric boundary …

    uiuc Repository record for Monte Carlo Simulation of Nanostructures: Semiconductor Devices to Ion Channels (opens in a new tab)

  19. Modeling and simulation of nano-scale transistor

    … of transistor technology such as FDSOI and FinFET have been the main driving force of semiconductor industry. As the node CD of modern transistor is shrinking down to sub-5 nm nowadays, novel device concept and new semiconductor material need new device model methodology and understanding of …

    udel Repository record for Modeling and simulation of nano-scale transistor (opens in a new tab)

  20. Antimonide-based III-V multigate transistors

    … has been pioneered and the first InGaSb FinFET has been demonstrated. Critical technological challenges for realizing InGaSb FinFETs have been overcome. First, a dry etching technique of heterostructures containing antimonide-based compounds has been developed. Etched fins and vertical …

    mit Repository record for Antimonide-based III-V multigate transistors (opens in a new tab)

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