Abstract
dc:description.abstract<p>This paper describes an analog-to-digital signal converter which varies its precision as a function of input slew rate (maximum signal rate of change), in order to best follow the input in real time. It uses Flash and Successive Approximation (SAR) conversion techniques in sequence.</p> <p>As part of the design, the concept of "total real-time optimization" is explored, where any delay at all is treated as an error (Error = Delay * Signal Slew Rate). This error metric is proposed for use in digital control systems. The ADC uses a 4-bit Flash converter in tandem with SAR logic that has variable precision (0 to 11 bits). This allows the Tandem ADC to switch from a fast, imprecise converter to a slow, precise converter. The level of precision is determined by the input’s peak rate of change, optimized for minimum real-time error; a secondary goal is to react quickly to input transient spikes.</p> <p>The implementation of the Tandem ADC is described, along with various issues which arise when designing such a converter and how they may be dealt with. These include Flash ADC inaccuracies, rounding issues, and system timing and synchronization.</p> <p>Most of the design is described down to the level of logic gates and related building blocks (e.g. latches and flip-flops), and various logic optimizations are used in the design to reduce calculation delays. The design also avoids active analog circuitry whenever possible – it can be almost entirely implemented with CMOS logic and passive analog components.</p>
Degree
thesis:*- Name thesis:degree_name
- MS in Electrical Engineering
- Discipline thesis:degree_discipline
- Electrical Engineering
- Year dc:date.available
- 2014
Author and committee
dc:creator, dc:contributor.*- Author dc:creator
-
- Parsons, Colton A
- Contributors dc:contributor
-
- Wayne Pilkington
Subjects
dc:subject × 7Identifiers
dc:identifier.*- Identifier
- 10.15368/theses.2014.100
- OAI identifier oai:identifier
- oai:digitalcommons.calpoly.edu:theses-2338