A Highly Abstracted Method of FPGA-Based Development for Secondary Surveillance Radar Transpond Detection

Traditional FPGA-based digital design is based on writing hardware definition language (HDL) code from scratch. Time to market, cost of development, and the level of training required for designers all can be reduced with a simplified and abstracted design strategy. This project intends to demonstrate a graphical user interface (GUI) layer of abstraction on top of existing commercially produced design aids including MATLAB, Simulink, and Xilinx System Generator. This project performs and demonstrates a specific implementation example of a Secondary Surveillance Radar (SSR) message decoder as proof-of-concept for the abstracted design method. The abstracted digital design methods shown in this project can be adapted for use in other areas of development and research including digital signal processing and communications.

Name thesis:degree_name

MS in Electrical Engineering

Discipline thesis:degree_discipline

Electrical Engineering

Year dc:date.available

2009

Author dc:creator

• Watt, James Penn

Contributors dc:contributor

• Dennis Derickson

• digital design
• HDL
• IFF
• Mode S
• SSR
• ViaSat
• Systems and Communications

Identifier

10.15368/theses.2009.92

OAI identifier oai:identifier

oai:digitalcommons.calpoly.edu:theses-1158